Design of a Library for DRAM Power Reduction in an Embedded Multi-task Kernel

Satomi Kobayashi, Akira Fukuda

Research output: Contribution to conferencePaperpeer-review

Abstract

This paper proposes a memory management library for DRAM power reduction cooperated with the scheduler in an embedded operating system. The main memory DRAMs have multi power mode status and consist of banks which are smaller in size than their total capacity. Their electrical power can be controlled with the unit of banks to perform read and write transactions. We study a method of dynamic power reduction in DRAMs without having to depend on any dedicated hardware. Simulation results explain good performance of our method with the algorithm of a minimum cost flow problem.

Original languageEnglish
Pages5-8
Number of pages4
Publication statusPublished - 2003
Event2003 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM 2003) - Victoria, B.C., Canada
Duration: Aug 28 2003Aug 30 2003

Other

Other2003 IEEE Pacific Rim Conference on Communications Computers and Signal Processing (PACRIM 2003)
CountryCanada
CityVictoria, B.C.
Period8/28/038/30/03

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Networks and Communications

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