Design of a Library for DRAM Power Reduction in an Embedded Multi-task Kernel

This paper proposes a memory management library for DRAM power reduction cooperated with the scheduler in an embedded operating system. The main memory DRAMs have multi power mode status and consist of banks which are smaller in size than their total capacity. Their electrical power can be controlled with the unit of banks to perform read and write transactions. We study a method of dynamic power reduction in DRAMs without having to depend on any dedicated hardware. Simulation results explain good performance of our method with the algorithm of a minimum cost flow problem.