Design of a lifting wavelet processor for one dimensional signal detection

Koichi Kuzume, Koichi Niijima, Shigeru Takano

    Research output: Contribution to journalConference articlepeer-review

    Abstract

    This paper presents the realization of a lifting wavelet processor for signal detection on a field programmable gate array (FPGA) device. This processor implements an algorithm for detecting target portions from a signal using an integer type Haar lifting wavelet transform (IHLWT), which we proposed. The VLSI can be designed using a small amount of circuitry, consisting of only 6 multipliers and 9 adders with a pipeline architecture. The VLSI is designed using Hardware Description Language (HDL) and is simulated on the FPGA in practice. The test scenarios covering several kinds of electrocardiogram (ECG) signals are examined thoroughly.

    Original languageEnglish
    Pages (from-to)II421-II424
    JournalMidwest Symposium on Circuits and Systems
    Volume2
    Publication statusPublished - 2004
    EventThe 2004 47th Midwest Symposium on Circuits and Systems - Conference Proceedings - Hiroshima, Japan
    Duration: Jul 25 2004Jul 28 2004

    All Science Journal Classification (ASJC) codes

    • Electronic, Optical and Magnetic Materials
    • Electrical and Electronic Engineering

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