Design of high-linearity amplifier for wireless LAN transceiver

O. Nizhnik, Ramesh Pokharel, Haruichi Kanaya, K. Yoshida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

High third- order intercept output point (OIP3) RF amplifier, suitable for cheap semiconductor technology is proposed. The circuit functionality simulated using Agilent ADS and parasitic components were taken into account using Assura RCX chip design software. Chip has designed for TSMC 0.35-um BiCMOS process. An OIP3 over +30dBm was achieved with a gain of 8 dB, noise figure 5dB, and a power consumption 80 mW. Amplifier is intended to be used in receiver and transmitter paths of the 802.11a/b/n wireless LAN front-end in 5 GHz band.

Original languageEnglish
Title of host publication2007 Asia-Pacific Microwave Conference, APMC
DOIs
Publication statusPublished - Dec 1 2007
EventAsia-Pacific Microwave Conference, APMC 2007 - Bangkok, Thailand
Duration: Dec 11 2007Dec 14 2007

Other

OtherAsia-Pacific Microwave Conference, APMC 2007
CountryThailand
CityBangkok
Period12/11/0712/14/07

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All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Nizhnik, O., Pokharel, R., Kanaya, H., & Yoshida, K. (2007). Design of high-linearity amplifier for wireless LAN transceiver. In 2007 Asia-Pacific Microwave Conference, APMC [4554554] https://doi.org/10.1109/APMC.2007.4554554