TY - GEN
T1 - Design of multi-layers DGS resonator for phase noise improvement of K-Band VCOs in 0.18 µm CMOS technology
AU - Mansour, Islam
AU - Aboualalaa, Mohamed
AU - Jahan, Nusrat
AU - Barakat, Adel
AU - Pokharel, Ramesh K.
AU - Allam, Ahmed
AU - Abdel-Rahman, Adel B.
AU - Abo-Zahhad, Mohammed
N1 - Funding Information:
This work is supported in part by a Grant-in-Aid for Scientific Research (C) (JP 16K06301) and in part by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Cadence and Keysight Corporations.
Publisher Copyright:
© 2018 IEEE
PY - 2019/1/22
Y1 - 2019/1/22
N2 - A novel technique for a low phase noise and compact K-band Voltage-Controlled Oscillator (VCO) using multi-layers DGS resonator is proposed. The proposed DGS resonator realizes an additional series resonance at the higher side of parallel resonance frequency, and this results in improving both the active and loaded quality factor of the resonator. The proposed resonator has active quality factor of 130 and a compact size of 0.009 mm 2 (0.000459 ? 2 ). Using the proposed DGS resonator in the VCO causes 9 dB improvement in the phase noise compared the VCO implemented using the conventional LC resonator. Two VCOs are designed using the method to illustrate the effect of the series resonance. The first VCO is designed three layers DGS resonator and the other VCO using two layers DGS resonator. The designs are implemented in 0.18 µm CMOS technology and consume 2.9 mW power, and from the post layout results, the first proposed VCO oscillates from 19.6 to 21.3 GHz (8.3 %) and has a phase noise of -113.2 dBc/Hz at 1 MHz offset frequency, and this results in the figure of merit (FoM) and FoM taking account of the tuning range to be -194.4 and -192.7 dB, respectively. The second VCO has a tuning range of 6.1 % and phase noise of -114 dBc/Hz @ 1 MHz offset at 19.6 GHz oscillation.
AB - A novel technique for a low phase noise and compact K-band Voltage-Controlled Oscillator (VCO) using multi-layers DGS resonator is proposed. The proposed DGS resonator realizes an additional series resonance at the higher side of parallel resonance frequency, and this results in improving both the active and loaded quality factor of the resonator. The proposed resonator has active quality factor of 130 and a compact size of 0.009 mm 2 (0.000459 ? 2 ). Using the proposed DGS resonator in the VCO causes 9 dB improvement in the phase noise compared the VCO implemented using the conventional LC resonator. Two VCOs are designed using the method to illustrate the effect of the series resonance. The first VCO is designed three layers DGS resonator and the other VCO using two layers DGS resonator. The designs are implemented in 0.18 µm CMOS technology and consume 2.9 mW power, and from the post layout results, the first proposed VCO oscillates from 19.6 to 21.3 GHz (8.3 %) and has a phase noise of -113.2 dBc/Hz at 1 MHz offset frequency, and this results in the figure of merit (FoM) and FoM taking account of the tuning range to be -194.4 and -192.7 dB, respectively. The second VCO has a tuning range of 6.1 % and phase noise of -114 dBc/Hz @ 1 MHz offset at 19.6 GHz oscillation.
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U2 - 10.1109/MWSCAS.2018.8623874
DO - 10.1109/MWSCAS.2018.8623874
M3 - Conference contribution
AN - SCOPUS:85062216979
T3 - Midwest Symposium on Circuits and Systems
SP - 178
EP - 181
BT - 2018 IEEE 61st International Midwest Symposium on Circuits and Systems, MWSCAS 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 61st IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2018
Y2 - 5 August 2018 through 8 August 2018
ER -