Abstract
This paper presents a digitally controlled oscillator (DCO) in Inductor-Capacitor (LC) topology with an enhanced frequency-steps and power consumption. Using special Fibonacci sequence method for optimizing capacitor sizes, this digitally-controlled oscillator (DCO) realizes frequency-tuning steps superior than a conventional DCO using binary sequence without increasing the power consumption. The proposed circuit is implemented in 0.18 um CMOS technology and tested. It has a center frequency of 7.9 GHz. The measured phase noise is 117.1 dBc/Hz(@1MHz offset) at carrier frequency of 7.7 GHz.
| Original language | English |
|---|---|
| Title of host publication | Asia-Pacific Microwave Conference Proceedings, APMC 2011 |
| Pages | 1634-1637 |
| Number of pages | 4 |
| Publication status | Published - Dec 1 2011 |
| Event | Asia-Pacific Microwave Conference, APMC 2011 - Melbourne, VIC, Australia Duration: Dec 5 2011 → Dec 8 2011 |
Publication series
| Name | Asia-Pacific Microwave Conference Proceedings, APMC |
|---|
Other
| Other | Asia-Pacific Microwave Conference, APMC 2011 |
|---|---|
| Country | Australia |
| City | Melbourne, VIC |
| Period | 12/5/11 → 12/8/11 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
Cite this
Development of 13 bit digitally controlled oscillator using fibonacci sequence in 0.18 um CMOS process. / Ishihara, M.; Pokharel, R. K.; Tomar, A.; Kanemoto, D.; Kanaya, H.; Yoshida, K.
Asia-Pacific Microwave Conference Proceedings, APMC 2011. 2011. p. 1634-1637 6174080 (Asia-Pacific Microwave Conference Proceedings, APMC).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Development of 13 bit digitally controlled oscillator using fibonacci sequence in 0.18 um CMOS process
AU - Ishihara, M.
AU - Pokharel, R. K.
AU - Tomar, A.
AU - Kanemoto, D.
AU - Kanaya, H.
AU - Yoshida, K.
PY - 2011/12/1
Y1 - 2011/12/1
N2 - This paper presents a digitally controlled oscillator (DCO) in Inductor-Capacitor (LC) topology with an enhanced frequency-steps and power consumption. Using special Fibonacci sequence method for optimizing capacitor sizes, this digitally-controlled oscillator (DCO) realizes frequency-tuning steps superior than a conventional DCO using binary sequence without increasing the power consumption. The proposed circuit is implemented in 0.18 um CMOS technology and tested. It has a center frequency of 7.9 GHz. The measured phase noise is 117.1 dBc/Hz(@1MHz offset) at carrier frequency of 7.7 GHz.
AB - This paper presents a digitally controlled oscillator (DCO) in Inductor-Capacitor (LC) topology with an enhanced frequency-steps and power consumption. Using special Fibonacci sequence method for optimizing capacitor sizes, this digitally-controlled oscillator (DCO) realizes frequency-tuning steps superior than a conventional DCO using binary sequence without increasing the power consumption. The proposed circuit is implemented in 0.18 um CMOS technology and tested. It has a center frequency of 7.9 GHz. The measured phase noise is 117.1 dBc/Hz(@1MHz offset) at carrier frequency of 7.7 GHz.
UR - http://www.scopus.com/inward/record.url?scp=84860500035&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84860500035&partnerID=8YFLogxK
M3 - Conference contribution
AN - SCOPUS:84860500035
SN - 9780858259744
T3 - Asia-Pacific Microwave Conference Proceedings, APMC
SP - 1634
EP - 1637
BT - Asia-Pacific Microwave Conference Proceedings, APMC 2011
ER -