TY - GEN
T1 - Development of 13 bit digitally controlled oscillator using fibonacci sequence in 0.18 um CMOS process
AU - Ishihara, M.
AU - Pokharel, R. K.
AU - Tomar, A.
AU - Kanemoto, D.
AU - Kanaya, H.
AU - Yoshida, K.
PY - 2011/12/1
Y1 - 2011/12/1
N2 - This paper presents a digitally controlled oscillator (DCO) in Inductor-Capacitor (LC) topology with an enhanced frequency-steps and power consumption. Using special Fibonacci sequence method for optimizing capacitor sizes, this digitally-controlled oscillator (DCO) realizes frequency-tuning steps superior than a conventional DCO using binary sequence without increasing the power consumption. The proposed circuit is implemented in 0.18 um CMOS technology and tested. It has a center frequency of 7.9 GHz. The measured phase noise is 117.1 dBc/Hz(@1MHz offset) at carrier frequency of 7.7 GHz.
AB - This paper presents a digitally controlled oscillator (DCO) in Inductor-Capacitor (LC) topology with an enhanced frequency-steps and power consumption. Using special Fibonacci sequence method for optimizing capacitor sizes, this digitally-controlled oscillator (DCO) realizes frequency-tuning steps superior than a conventional DCO using binary sequence without increasing the power consumption. The proposed circuit is implemented in 0.18 um CMOS technology and tested. It has a center frequency of 7.9 GHz. The measured phase noise is 117.1 dBc/Hz(@1MHz offset) at carrier frequency of 7.7 GHz.
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M3 - Conference contribution
AN - SCOPUS:84860500035
SN - 9780858259744
T3 - Asia-Pacific Microwave Conference Proceedings, APMC
SP - 1634
EP - 1637
BT - Asia-Pacific Microwave Conference Proceedings, APMC 2011
T2 - Asia-Pacific Microwave Conference, APMC 2011
Y2 - 5 December 2011 through 8 December 2011
ER -