Development of 13 bit digitally controlled oscillator using fibonacci sequence in 0.18 um CMOS process

M. Ishihara; R. K. Pokharel; A. Tomar; D. Kanemoto; H. Kanaya; K. Yoshida

Development of 13 bit digitally controlled oscillator using fibonacci sequence in 0.18 um CMOS process

M. Ishihara, R. K. Pokharel, A. Tomar, D. Kanemoto, H. Kanaya, K. Yoshida

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

This paper presents a digitally controlled oscillator (DCO) in Inductor-Capacitor (LC) topology with an enhanced frequency-steps and power consumption. Using special Fibonacci sequence method for optimizing capacitor sizes, this digitally-controlled oscillator (DCO) realizes frequency-tuning steps superior than a conventional DCO using binary sequence without increasing the power consumption. The proposed circuit is implemented in 0.18 um CMOS technology and tested. It has a center frequency of 7.9 GHz. The measured phase noise is 117.1 dBc/Hz(@1MHz offset) at carrier frequency of 7.7 GHz.

Original language	English
Title of host publication	Asia-Pacific Microwave Conference Proceedings, APMC 2011
Pages	1634-1637
Number of pages	4
Publication status	Published - Dec 1 2011
Event	Asia-Pacific Microwave Conference, APMC 2011 - Melbourne, VIC, Australia Duration: Dec 5 2011 → Dec 8 2011

Publication series

Name	Asia-Pacific Microwave Conference Proceedings, APMC

Other

Other	Asia-Pacific Microwave Conference, APMC 2011
Country	Australia
City	Melbourne, VIC
Period	12/5/11 → 12/8/11

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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Development of 13 bit digitally controlled oscillator using fibonacci sequence in 0.18 um CMOS process. / Ishihara, M.; Pokharel, R. K.; Tomar, A.; Kanemoto, D.; Kanaya, H.; Yoshida, K.

Asia-Pacific Microwave Conference Proceedings, APMC 2011. 2011. p. 1634-1637 6174080 (Asia-Pacific Microwave Conference Proceedings, APMC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Ishihara, M, Pokharel, RK, Tomar, A, Kanemoto, D, Kanaya, H & Yoshida, K 2011, Development of 13 bit digitally controlled oscillator using fibonacci sequence in 0.18 um CMOS process. in Asia-Pacific Microwave Conference Proceedings, APMC 2011., 6174080, Asia-Pacific Microwave Conference Proceedings, APMC, pp. 1634-1637, Asia-Pacific Microwave Conference, APMC 2011, Melbourne, VIC, Australia, 12/5/11.

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abstract = "This paper presents a digitally controlled oscillator (DCO) in Inductor-Capacitor (LC) topology with an enhanced frequency-steps and power consumption. Using special Fibonacci sequence method for optimizing capacitor sizes, this digitally-controlled oscillator (DCO) realizes frequency-tuning steps superior than a conventional DCO using binary sequence without increasing the power consumption. The proposed circuit is implemented in 0.18 um CMOS technology and tested. It has a center frequency of 7.9 GHz. The measured phase noise is 117.1 dBc/Hz(@1MHz offset) at carrier frequency of 7.7 GHz.",

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AU - Yoshida, K.

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AB - This paper presents a digitally controlled oscillator (DCO) in Inductor-Capacitor (LC) topology with an enhanced frequency-steps and power consumption. Using special Fibonacci sequence method for optimizing capacitor sizes, this digitally-controlled oscillator (DCO) realizes frequency-tuning steps superior than a conventional DCO using binary sequence without increasing the power consumption. The proposed circuit is implemented in 0.18 um CMOS technology and tested. It has a center frequency of 7.9 GHz. The measured phase noise is 117.1 dBc/Hz(@1MHz offset) at carrier frequency of 7.7 GHz.

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