TY - JOUR
T1 - Development of a high-performance control system by decentralization with reflective memory on QUEST
AU - Hasegawa, Makoto
AU - Nakamura, Kazuo
AU - Zushi, Hideki
AU - Hanada, Kazuaki
AU - Fujisawa, Akihide
AU - Mitarai, Osamu
AU - Tokunaga, Kazutoshi
AU - Idei, Hiroshi
AU - Nagashima, Yoshihiko
AU - Kawasaki, Shoji
AU - Nakashima, Hisatoshi
AU - Higashijima, Aki
N1 - Publisher Copyright:
© 2015 Elsevier B.V. All rights reserved.
Copyright:
Copyright 2015 Elsevier B.V., All rights reserved.
PY - 2015/10/1
Y1 - 2015/10/1
N2 - The plasma control system (PCS) of QUEST was a centralized system, which lost its scalability because of the overload imposed on its central processing unit (CPU) of the PCS, making it impossible to add new functions. Thus, the PCS is distributed into a main workstation (WS) and subsystem (SS) with a reflective memory (RFM) in order to share data between these systems so as to mitigate the load on each system. As a result, 128 double-precision floating-point numbers (DBLs) can be transferred from the SS to the WS with a maximum latency of 250 μs. The WS and the SS each have quad-core CPUs, and tasks are executed in parallel. Although one of the four cores is intermittently occupied by up to 90% by this transaction, the occupation is normally 60%. A time correction procedure is used to map the recorded data sets on the WS and the SS to a common time base by referring to the time difference between two systems.
AB - The plasma control system (PCS) of QUEST was a centralized system, which lost its scalability because of the overload imposed on its central processing unit (CPU) of the PCS, making it impossible to add new functions. Thus, the PCS is distributed into a main workstation (WS) and subsystem (SS) with a reflective memory (RFM) in order to share data between these systems so as to mitigate the load on each system. As a result, 128 double-precision floating-point numbers (DBLs) can be transferred from the SS to the WS with a maximum latency of 250 μs. The WS and the SS each have quad-core CPUs, and tasks are executed in parallel. Although one of the four cores is intermittently occupied by up to 90% by this transaction, the occupation is normally 60%. A time correction procedure is used to map the recorded data sets on the WS and the SS to a common time base by referring to the time difference between two systems.
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U2 - 10.1016/j.fusengdes.2015.06.054
DO - 10.1016/j.fusengdes.2015.06.054
M3 - Article
AN - SCOPUS:84942820609
SN - 0920-3796
VL - 96-97
SP - 629
EP - 632
JO - Fusion Engineering and Design
JF - Fusion Engineering and Design
ER -