Development of low power DAC with pseudo Fibonacci sequence

Ryota Kubokawa, Takashi Ohshima, Abhishek Tomar, Ramesh Pokharel, Haruichi Kanaya, Keiji Yoshida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A 12-bit Digital-analog converter (DAC) with pseudo Fibonacci sequence was fabricated in a 0.18μm CMOS technology. Proposed 12-bit DAC is composed of a 6-bit pseudo Fibonacci sequence and 6bit unary sequence. The power consumption of the proposed DAC is expected lower than that of conventional binary and unary DAC. The simulated power consumption of proposed 12-bit DAC is 40mV at 3.3V supply voltage. Also we fabricated the prototype 6-bit DAC with pseudo Fibonacci sequence and tested. The measured power consumption is very low and almost the same value as a simulated value.

Original languageEnglish
Title of host publicationProceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Pages370-373
Number of pages4
DOIs
Publication statusPublished - 2010
Event2010 Asia Pacific Conference on Circuit and System, APCCAS 2010 - Kuala Lumpur, Malaysia
Duration: Dec 6 2010Dec 9 2010

Other

Other2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Country/TerritoryMalaysia
CityKuala Lumpur
Period12/6/1012/9/10

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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