Development of strained Si-SiGe-on-insulator wafers for high speed ULSI

Hiroshi Nakashima, Masanobu Miyao, Masahiko Nakamae, Tanemasa Asano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Strain relaxation process of SiGe-on-insulator (SGOI) structures in the oxidation induced Ge condensation method was investigated as a function of SiGe thickness. Complete relaxation was obtained for SiGe layer having the thickness of more than 60 nm, leading to the establishment of highly relaxed SGOI wafer fabrication. The photoluminescence evaluation of the strained Si/SGOI wafers showed high Ge fraction degrades crystallinity of St-Si/SGOI wafer, and high Ge condensation temperature is beneficial to the crystallinity enhancement. CMOS inverters and ring oscillators were fabricated to evaluate the impact of Strained-Si/SGOI on the device performance. The signal propagation speed of the CMOS on the St-Si/SGOI wafer was twice as high as that of the Si-on-insulator CMOS.

Original languageEnglish
Title of host publicationICSICT-2006
Subtitle of host publication2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
Pages100-103
Number of pages4
DOIs
Publication statusPublished - 2007
EventICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
Duration: Oct 23 2006Oct 26 2006

Other

OtherICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
CountryChina
CityShanghai
Period10/23/0610/26/06

Fingerprint

Condensation
Strain relaxation
Relaxation processes
Photoluminescence
Fabrication
Oxidation
Temperature

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Nakashima, H., Miyao, M., Nakamae, M., & Asano, T. (2007). Development of strained Si-SiGe-on-insulator wafers for high speed ULSI. In ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings (pp. 100-103). [4098032] https://doi.org/10.1109/ICSICT.2006.306088

Development of strained Si-SiGe-on-insulator wafers for high speed ULSI. / Nakashima, Hiroshi; Miyao, Masanobu; Nakamae, Masahiko; Asano, Tanemasa.

ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2007. p. 100-103 4098032.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nakashima, H, Miyao, M, Nakamae, M & Asano, T 2007, Development of strained Si-SiGe-on-insulator wafers for high speed ULSI. in ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings., 4098032, pp. 100-103, ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Shanghai, China, 10/23/06. https://doi.org/10.1109/ICSICT.2006.306088
Nakashima H, Miyao M, Nakamae M, Asano T. Development of strained Si-SiGe-on-insulator wafers for high speed ULSI. In ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2007. p. 100-103. 4098032 https://doi.org/10.1109/ICSICT.2006.306088
Nakashima, Hiroshi ; Miyao, Masanobu ; Nakamae, Masahiko ; Asano, Tanemasa. / Development of strained Si-SiGe-on-insulator wafers for high speed ULSI. ICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings. 2007. pp. 100-103
@inproceedings{3f48be7c9666442298c65faba9032bcd,
title = "Development of strained Si-SiGe-on-insulator wafers for high speed ULSI",
abstract = "Strain relaxation process of SiGe-on-insulator (SGOI) structures in the oxidation induced Ge condensation method was investigated as a function of SiGe thickness. Complete relaxation was obtained for SiGe layer having the thickness of more than 60 nm, leading to the establishment of highly relaxed SGOI wafer fabrication. The photoluminescence evaluation of the strained Si/SGOI wafers showed high Ge fraction degrades crystallinity of St-Si/SGOI wafer, and high Ge condensation temperature is beneficial to the crystallinity enhancement. CMOS inverters and ring oscillators were fabricated to evaluate the impact of Strained-Si/SGOI on the device performance. The signal propagation speed of the CMOS on the St-Si/SGOI wafer was twice as high as that of the Si-on-insulator CMOS.",
author = "Hiroshi Nakashima and Masanobu Miyao and Masahiko Nakamae and Tanemasa Asano",
year = "2007",
doi = "10.1109/ICSICT.2006.306088",
language = "English",
isbn = "1424401615",
pages = "100--103",
booktitle = "ICSICT-2006",

}

TY - GEN

T1 - Development of strained Si-SiGe-on-insulator wafers for high speed ULSI

AU - Nakashima, Hiroshi

AU - Miyao, Masanobu

AU - Nakamae, Masahiko

AU - Asano, Tanemasa

PY - 2007

Y1 - 2007

N2 - Strain relaxation process of SiGe-on-insulator (SGOI) structures in the oxidation induced Ge condensation method was investigated as a function of SiGe thickness. Complete relaxation was obtained for SiGe layer having the thickness of more than 60 nm, leading to the establishment of highly relaxed SGOI wafer fabrication. The photoluminescence evaluation of the strained Si/SGOI wafers showed high Ge fraction degrades crystallinity of St-Si/SGOI wafer, and high Ge condensation temperature is beneficial to the crystallinity enhancement. CMOS inverters and ring oscillators were fabricated to evaluate the impact of Strained-Si/SGOI on the device performance. The signal propagation speed of the CMOS on the St-Si/SGOI wafer was twice as high as that of the Si-on-insulator CMOS.

AB - Strain relaxation process of SiGe-on-insulator (SGOI) structures in the oxidation induced Ge condensation method was investigated as a function of SiGe thickness. Complete relaxation was obtained for SiGe layer having the thickness of more than 60 nm, leading to the establishment of highly relaxed SGOI wafer fabrication. The photoluminescence evaluation of the strained Si/SGOI wafers showed high Ge fraction degrades crystallinity of St-Si/SGOI wafer, and high Ge condensation temperature is beneficial to the crystallinity enhancement. CMOS inverters and ring oscillators were fabricated to evaluate the impact of Strained-Si/SGOI on the device performance. The signal propagation speed of the CMOS on the St-Si/SGOI wafer was twice as high as that of the Si-on-insulator CMOS.

UR - http://www.scopus.com/inward/record.url?scp=34547314291&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=34547314291&partnerID=8YFLogxK

U2 - 10.1109/ICSICT.2006.306088

DO - 10.1109/ICSICT.2006.306088

M3 - Conference contribution

SN - 1424401615

SN - 9781424401611

SP - 100

EP - 103

BT - ICSICT-2006

ER -