Development of strained Si-SiGe-on-insulator wafers for high speed ULSI

Hiroshi Nakashima, Masanobu Miyao, Masahiko Nakamae, Tanemasa Asano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Strain relaxation process of SiGe-on-insulator (SGOI) structures in the oxidation induced Ge condensation method was investigated as a function of SiGe thickness. Complete relaxation was obtained for SiGe layer having the thickness of more than 60 nm, leading to the establishment of highly relaxed SGOI wafer fabrication. The photoluminescence evaluation of the strained Si/SGOI wafers showed high Ge fraction degrades crystallinity of St-Si/SGOI wafer, and high Ge condensation temperature is beneficial to the crystallinity enhancement. CMOS inverters and ring oscillators were fabricated to evaluate the impact of Strained-Si/SGOI on the device performance. The signal propagation speed of the CMOS on the St-Si/SGOI wafer was twice as high as that of the Si-on-insulator CMOS.

Original languageEnglish
Title of host publicationICSICT-2006
Subtitle of host publication2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings
PublisherIEEE Computer Society
Pages100-103
Number of pages4
ISBN (Print)1424401615, 9781424401611
DOIs
Publication statusPublished - Jan 1 2006
EventICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology - Shanghai, China
Duration: Oct 23 2006Oct 26 2006

Publication series

NameICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology, Proceedings

Other

OtherICSICT-2006: 2006 8th International Conference on Solid-State and Integrated Circuit Technology
CountryChina
CityShanghai
Period10/23/0610/26/06

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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