Digitally controlled ring oscillator using fraction-based series optimization for inductorless reconfigurable all-digital PLL

Ramesh Pokharel, Satoshi Hamada, Abhishek Tomar, Shashank Lingala, Prapto Nugroho, Haruichi Kanaya, Keiji Yoshida

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Design and implementation of a CMOS multiphase 10b digitally controlled oscillator (DCO) in ring topology that employs fraction-based series to optimize the transistors size, are presented. One of the advantages of using fraction-based series is that it can reduce the power consumption compared to the binary series without any cost of tuning range and phase noise. The proposed DCO, which was implemented on 0.18 μm CMOS technology, features the tuning frequency 600 MHz to 4.27 GHz with power consumption from 10 mW-40 mW. The measured phase noise is -114.7 dBc/Hz (@4 MHz offset) of the carrier frequency 2.75 GHz.

Original languageEnglish
Title of host publication2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Digest of Papers
Pages69-72
Number of pages4
DOIs
Publication statusPublished - Mar 25 2011
Event2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Phoenix, AR, United States
Duration: Jan 16 2011Jan 19 2011

Other

Other2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011
CountryUnited States
CityPhoenix, AR
Period1/16/111/19/11

Fingerprint

Phase locked loops
Phase noise
Electric power utilization
Tuning
Transistors
Topology
Costs

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Pokharel, R., Hamada, S., Tomar, A., Lingala, S., Nugroho, P., Kanaya, H., & Yoshida, K. (2011). Digitally controlled ring oscillator using fraction-based series optimization for inductorless reconfigurable all-digital PLL. In 2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Digest of Papers (pp. 69-72). [5719321] https://doi.org/10.1109/SIRF.2011.5719321

Digitally controlled ring oscillator using fraction-based series optimization for inductorless reconfigurable all-digital PLL. / Pokharel, Ramesh; Hamada, Satoshi; Tomar, Abhishek; Lingala, Shashank; Nugroho, Prapto; Kanaya, Haruichi; Yoshida, Keiji.

2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Digest of Papers. 2011. p. 69-72 5719321.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Pokharel, R, Hamada, S, Tomar, A, Lingala, S, Nugroho, P, Kanaya, H & Yoshida, K 2011, Digitally controlled ring oscillator using fraction-based series optimization for inductorless reconfigurable all-digital PLL. in 2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Digest of Papers., 5719321, pp. 69-72, 2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011, Phoenix, AR, United States, 1/16/11. https://doi.org/10.1109/SIRF.2011.5719321
Pokharel R, Hamada S, Tomar A, Lingala S, Nugroho P, Kanaya H et al. Digitally controlled ring oscillator using fraction-based series optimization for inductorless reconfigurable all-digital PLL. In 2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Digest of Papers. 2011. p. 69-72. 5719321 https://doi.org/10.1109/SIRF.2011.5719321
Pokharel, Ramesh ; Hamada, Satoshi ; Tomar, Abhishek ; Lingala, Shashank ; Nugroho, Prapto ; Kanaya, Haruichi ; Yoshida, Keiji. / Digitally controlled ring oscillator using fraction-based series optimization for inductorless reconfigurable all-digital PLL. 2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Digest of Papers. 2011. pp. 69-72
@inproceedings{f074ac1e27d24a93b8cbead838c85d80,
title = "Digitally controlled ring oscillator using fraction-based series optimization for inductorless reconfigurable all-digital PLL",
abstract = "Design and implementation of a CMOS multiphase 10b digitally controlled oscillator (DCO) in ring topology that employs fraction-based series to optimize the transistors size, are presented. One of the advantages of using fraction-based series is that it can reduce the power consumption compared to the binary series without any cost of tuning range and phase noise. The proposed DCO, which was implemented on 0.18 μm CMOS technology, features the tuning frequency 600 MHz to 4.27 GHz with power consumption from 10 mW-40 mW. The measured phase noise is -114.7 dBc/Hz (@4 MHz offset) of the carrier frequency 2.75 GHz.",
author = "Ramesh Pokharel and Satoshi Hamada and Abhishek Tomar and Shashank Lingala and Prapto Nugroho and Haruichi Kanaya and Keiji Yoshida",
year = "2011",
month = "3",
day = "25",
doi = "10.1109/SIRF.2011.5719321",
language = "English",
isbn = "9781424480593",
pages = "69--72",
booktitle = "2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Digest of Papers",

}

TY - GEN

T1 - Digitally controlled ring oscillator using fraction-based series optimization for inductorless reconfigurable all-digital PLL

AU - Pokharel, Ramesh

AU - Hamada, Satoshi

AU - Tomar, Abhishek

AU - Lingala, Shashank

AU - Nugroho, Prapto

AU - Kanaya, Haruichi

AU - Yoshida, Keiji

PY - 2011/3/25

Y1 - 2011/3/25

N2 - Design and implementation of a CMOS multiphase 10b digitally controlled oscillator (DCO) in ring topology that employs fraction-based series to optimize the transistors size, are presented. One of the advantages of using fraction-based series is that it can reduce the power consumption compared to the binary series without any cost of tuning range and phase noise. The proposed DCO, which was implemented on 0.18 μm CMOS technology, features the tuning frequency 600 MHz to 4.27 GHz with power consumption from 10 mW-40 mW. The measured phase noise is -114.7 dBc/Hz (@4 MHz offset) of the carrier frequency 2.75 GHz.

AB - Design and implementation of a CMOS multiphase 10b digitally controlled oscillator (DCO) in ring topology that employs fraction-based series to optimize the transistors size, are presented. One of the advantages of using fraction-based series is that it can reduce the power consumption compared to the binary series without any cost of tuning range and phase noise. The proposed DCO, which was implemented on 0.18 μm CMOS technology, features the tuning frequency 600 MHz to 4.27 GHz with power consumption from 10 mW-40 mW. The measured phase noise is -114.7 dBc/Hz (@4 MHz offset) of the carrier frequency 2.75 GHz.

UR - http://www.scopus.com/inward/record.url?scp=79952844051&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79952844051&partnerID=8YFLogxK

U2 - 10.1109/SIRF.2011.5719321

DO - 10.1109/SIRF.2011.5719321

M3 - Conference contribution

AN - SCOPUS:79952844051

SN - 9781424480593

SP - 69

EP - 72

BT - 2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, SiRF 2011 - Digest of Papers

ER -