Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization

Ryohei Sato, Koichi Kakimoto, Wataru Saito, Shin Ichi Nishizawa

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper shows a new process guideline of high thermal budget process with Si 300 mm wafer in order to eliminate the dislocations. In the case of IGBT, high thermal budget process such as oxidation, diffusion, etc., cause large stress in wafer, and make dislocation propagation, slip, then degrade the device performance and yield. This degradation is enhanced with increasing wafer diameter, and becomes more serious for 300 mm process than that of 200 mm. We clarify the relation between the process condition (time-temperature profile) and dislocation behavior quantitatively under high thermal budget process, and propose the guideline to optimize the process condition. The optimized process minimizes the dislocation propagation in 300 mm Si wafer as same as that in 200 mm Si wafer with the conventional process condition.

Original languageEnglish
Title of host publicationProceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages494-497
Number of pages4
ISBN (Electronic)9781728148366
DOIs
Publication statusPublished - Sep 2020
Event32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020 - Virtual, Online, Austria
Duration: Sep 13 2020Sep 18 2020

Publication series

NameProceedings of the International Symposium on Power Semiconductor Devices and ICs
Volume2020-September
ISSN (Print)1063-6854

Conference

Conference32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020
CountryAustria
CityVirtual, Online
Period9/13/209/18/20

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Sato, R., Kakimoto, K., Saito, W., & Nishizawa, S. I. (2020). Dislocation Propagation in Si 300 mm Wafer during High Thermal Budget Process and Its Optimization. In Proceedings of the 2020 32nd International Symposium on Power Semiconductor Devices and ICs, ISPSD 2020 (pp. 494-497). [9170035] (Proceedings of the International Symposium on Power Semiconductor Devices and ICs; Vol. 2020-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISPSD46842.2020.9170035