Dynamically variable line-size cache exploiting high on-chip memory bandwidth of merged DRAM/logic LSIs

Inoue Koji, Koji Kai, Kazuaki Murakami

Research output: Contribution to conferencePaperpeer-review

19 Citations (Scopus)

Abstract

This paper proposes a novel cache architecture suitable for merged DRAM/logic LSIs, which is called `dynamically variable line-size cache (D-VLS cache)'. The D-VLS cache can optimize its line-size according to the characteristic of programs, and attempts to improve the performance by exploiting the high on-chip memory bandwidth. In our evaluation, it is observed that the performance improvement achieved by a direct-mapped D-VLS cache is about 27%, compared to a conventional direct-mapped cache with fixed 32-byte lines.

Original languageEnglish
Pages218-222
Number of pages5
Publication statusPublished - Jan 1 1999
EventProceedings of the 1999 5th International Symposium on High-Performance Computer Architecture, HPCA - Orlando, FL, USA
Duration: Jan 9 1999Jan 13 1999

Other

OtherProceedings of the 1999 5th International Symposium on High-Performance Computer Architecture, HPCA
CityOrlando, FL, USA
Period1/9/991/13/99

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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