Efficient equivalence checker for combinational circuits

Yusuke Matsunaga

Efficient equivalence checker for combinational circuits

Research output: Contribution to journal › Conference article

Abstract

This paper describes a novel equivalence checking method for combinational circuits, which utilizes relations among internal signals represented by binary decision diagrams. To verify circuits efficiently, a proper set of internal signals that are independent with each other should be chosen. A heuristic based on analysis of circuit structure is proposed to select such a set of internal signals. The proposed verifier requires only a minute for equivalence checking of all the ISCAS'85 benchmarks on SUN-4/10.

Original language	English
Pages (from-to)	629-634
Number of pages	6
Journal	Proceedings - Design Automation Conference
Publication status	Published - Jan 1 1996
Externally published	Yes
Event	Proceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA Duration: Jun 3 1996 → Jun 7 1996

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All Science Journal Classification (ASJC) codes

Hardware and Architecture
Control and Systems Engineering

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Matsunaga, Y. (1996). Efficient equivalence checker for combinational circuits. Proceedings - Design Automation Conference, 629-634.

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AB - This paper describes a novel equivalence checking method for combinational circuits, which utilizes relations among internal signals represented by binary decision diagrams. To verify circuits efficiently, a proper set of internal signals that are independent with each other should be chosen. A heuristic based on analysis of circuit structure is proposed to select such a set of internal signals. The proposed verifier requires only a minute for equivalence checking of all the ISCAS'85 benchmarks on SUN-4/10.

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Efficient equivalence checker for combinational circuits

Abstract

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All Science Journal Classification (ASJC) codes

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