Efficient equivalence checker for combinational circuits

Yusuke Matsunaga

doi:10.1145/240518.240637

Efficient equivalence checker for combinational circuits

Yusuke Matsunaga

Research output: Contribution to journal › Conference article › peer-review

54 Citations (Scopus)

Abstract

This paper describes a novel equivalence checking method for combinational circuits, which utilizes relations among internal signals represented by binary decision diagrams. To verify circuits efficiently, a proper set of internal signals that are independent with each other should be chosen. A heuristic based on analysis of circuit structure is proposed to select such a set of internal signals. The proposed verifier requires only a minute for equivalence checking of all the ISCAS'85 benchmarks on SUN-4/10.

Original language	English
Pages (from-to)	629-634
Number of pages	6
Journal	Proceedings - Design Automation Conference
DOIs	https://doi.org/10.1145/240518.240637
Publication status	Published - 1996
Externally published	Yes
Event	Proceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA Duration: Jun 3 1996 → Jun 7 1996

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Control and Systems Engineering

Access to Document

10.1145/240518.240637

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title = "Efficient equivalence checker for combinational circuits",

abstract = "This paper describes a novel equivalence checking method for combinational circuits, which utilizes relations among internal signals represented by binary decision diagrams. To verify circuits efficiently, a proper set of internal signals that are independent with each other should be chosen. A heuristic based on analysis of circuit structure is proposed to select such a set of internal signals. The proposed verifier requires only a minute for equivalence checking of all the ISCAS'85 benchmarks on SUN-4/10.",

author = "Yusuke Matsunaga",

year = "1996",

doi = "10.1145/240518.240637",

language = "English",

pages = "629--634",

journal = "Proceedings - Design Automation Conference",

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note = "Proceedings of the 1996 33rd Annual Design Automation Conference ; Conference date: 03-06-1996 Through 07-06-1996",

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AB - This paper describes a novel equivalence checking method for combinational circuits, which utilizes relations among internal signals represented by binary decision diagrams. To verify circuits efficiently, a proper set of internal signals that are independent with each other should be chosen. A heuristic based on analysis of circuit structure is proposed to select such a set of internal signals. The proposed verifier requires only a minute for equivalence checking of all the ISCAS'85 benchmarks on SUN-4/10.

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JF - Proceedings - Design Automation Conference

SN - 0738-100X

T2 - Proceedings of the 1996 33rd Annual Design Automation Conference

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