Embedded system cost optimization via data path width adjustment

Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura

Research output: Contribution to journalArticle

6 Citations (Scopus)

Abstract

Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator, we show that there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.

Original languageEnglish
Pages (from-to)974-981
Number of pages8
JournalIEICE Transactions on Information and Systems
VolumeE80-D
Issue number10
Publication statusPublished - Jan 1 1997

Fingerprint

Computer peripheral equipment
Cost reduction
Application programs
Embedded systems
Computer hardware
Program processors
Computer systems
Data storage equipment
Economics
Costs

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

Cite this

Shackleford, B., Yasuda, M., Okushi, E., Koizumi, H., Tomiyama, H., Inoue, A., & Yasuura, H. (1997). Embedded system cost optimization via data path width adjustment. IEICE Transactions on Information and Systems, E80-D(10), 974-981.

Embedded system cost optimization via data path width adjustment. / Shackleford, Barry; Yasuda, Mitsuhiro; Okushi, Etsuko; Koizumi, Hisao; Tomiyama, Hiroyuki; Inoue, Akihiko; Yasuura, Hiroto.

In: IEICE Transactions on Information and Systems, Vol. E80-D, No. 10, 01.01.1997, p. 974-981.

Research output: Contribution to journalArticle

Shackleford, B, Yasuda, M, Okushi, E, Koizumi, H, Tomiyama, H, Inoue, A & Yasuura, H 1997, 'Embedded system cost optimization via data path width adjustment', IEICE Transactions on Information and Systems, vol. E80-D, no. 10, pp. 974-981.
Shackleford B, Yasuda M, Okushi E, Koizumi H, Tomiyama H, Inoue A et al. Embedded system cost optimization via data path width adjustment. IEICE Transactions on Information and Systems. 1997 Jan 1;E80-D(10):974-981.
Shackleford, Barry ; Yasuda, Mitsuhiro ; Okushi, Etsuko ; Koizumi, Hisao ; Tomiyama, Hiroyuki ; Inoue, Akihiko ; Yasuura, Hiroto. / Embedded system cost optimization via data path width adjustment. In: IEICE Transactions on Information and Systems. 1997 ; Vol. E80-D, No. 10. pp. 974-981.
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