Embedded system cost optimization via data path width adjustment

Barry Shackleford, Mitsuhiro Yasuda, Etsuko Okushi, Hisao Koizumi, Hiroyuki Tomiyama, Akihiko Inoue, Hiroto Yasuura

Research output: Contribution to journalArticlepeer-review

6 Citations (Scopus)

Abstract

Entire systems embedded in a chip and consisting of a processor, memory, and system-specific peripheral hardware are now commonly contained in commodity electronic devices. Cost minimization of these systems is of paramount economic importance to manufactures of these devices. By employing a variable configuration processor in conjunction with a multi-precision compiler generator, we show that there are situations in which considerable system cost reduction can be obtained by synthesizing a CPU that is narrower than the largest variable in the application program.

Original languageEnglish
Pages (from-to)974-981
Number of pages8
JournalIEICE Transactions on Information and Systems
VolumeE80-D
Issue number10
Publication statusPublished - Jan 1 1997

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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