Enhancements of a circuit-level timing speculation technique and their evaluations using a co-simulation environment

Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura

Research output: Contribution to journalArticlepeer-review

1 Citation (Scopus)

Abstract

A deep submicron semiconductor technology has increased process variations. This fact makes the estimate of the worst-case design margin difficult. In order to realize robust designs, we are investigating such a typical-case design methodology, which we call Constructive Timing Violation (CTV). In the CTV-based design, we can relax timing constraints. However, relaxing timing constraints might cause some timing errors. While we have applied the CTV-based design to a processor, unfortunately, the timing error recovery has serious impact on processor performance. In this paper, we investigate enhancement techniques of the CTV-based design. In addition, in order to accurately evaluate the CTV- based design, we build a co-simulation framework to consider circuit delay at the architectural level. From the co-simulation results, we find the performance penalty is significantly reduced by the enhancement techniques.

Original languageEnglish
Pages (from-to)483-491
Number of pages9
JournalIEICE Transactions on Electronics
VolumeE92-C
Issue number4
DOIs
Publication statusPublished - 2009

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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