Enhancing a manycore-oriented compressed cache for GPGPU

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

GPUS can achieve high performance by exploiting massive-thread parallelism. However, some factors limit performance on GPUS, one of which is the negative effects of L1 cache misses. In some applications, GPUS are likely to suffer from L1 cache conflicts because a large number of cores share a small L1 cache capacity. A cache architecture that is based on data compression is a strong candidate for solving this problem as it can reduce the number of cache misses. Unlike previous studies, our data compression scheme attempts to exploit the value locality existing within not only intra cache lines but also inter cache lines. We enhance the structure of a last-level compression cache proposed for general purpose manycore processors to optimize against shared L1 caches on GPUS. The experimental results reveal that our proposal outperforms the other compression cache for GPUS by 11 points on average.

Original languageEnglish
Title of host publicationProceedings of International Conference on High Performance Computing in Asia-Pacific Region, HPC Asia 2020
PublisherAssociation for Computing Machinery
Pages22-31
Number of pages10
ISBN (Electronic)9781450372367
DOIs
Publication statusPublished - Jan 15 2020
Event2020 International Conference on High Performance Computing in Asia-Pacific Region, HPC Asia 2020 - Fukuoka, Japan
Duration: Jan 15 2020Jan 17 2020

Publication series

NameACM International Conference Proceeding Series

Conference

Conference2020 International Conference on High Performance Computing in Asia-Pacific Region, HPC Asia 2020
Country/TerritoryJapan
CityFukuoka
Period1/15/201/17/20

All Science Journal Classification (ASJC) codes

  • Human-Computer Interaction
  • Computer Networks and Communications
  • Computer Vision and Pattern Recognition
  • Software

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