Estimation of frequency, power and phase using modified digital phase locked loop

M. Saber, Y. Jitsumatsu, M. T.A. Khan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a method which can estimate frequency, power and phase of received signal corrupted with additive white Gaussian noise (AWGN) in large frequency offset environment. Proposed method consists of two loops, each loop is similar to a phase-locked loop (PLL). Proposed structure solves the problems of conventional PLL such as limited estimation range, long settling time, overshoot, high frequency ripples and instability. Traditional inability of PLL to synchronize signals with large frequency offset is also removed in this method. Furthermore, proposed architecture along with providing stability, ensures fast tracking of any changes in input frequency. Proposed method is also implemented using field programmable gate array (FPGA), it consumes 201 mW and works at 197 MHz.

Original languageEnglish
Title of host publication2012 International Conference on Systems and Informatics, ICSAI 2012
Pages1601-1605
Number of pages5
DOIs
Publication statusPublished - Jul 30 2012
Event2012 International Conference on Systems and Informatics, ICSAI 2012 - Yantai, China
Duration: May 19 2012May 20 2012

Publication series

Name2012 International Conference on Systems and Informatics, ICSAI 2012

Other

Other2012 International Conference on Systems and Informatics, ICSAI 2012
CountryChina
CityYantai
Period5/19/125/20/12

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All Science Journal Classification (ASJC) codes

  • Information Systems

Cite this

Saber, M., Jitsumatsu, Y., & Khan, M. T. A. (2012). Estimation of frequency, power and phase using modified digital phase locked loop. In 2012 International Conference on Systems and Informatics, ICSAI 2012 (pp. 1601-1605). [6223346] (2012 International Conference on Systems and Informatics, ICSAI 2012). https://doi.org/10.1109/ICSAI.2012.6223346