Evaluation of Residual Stress of Embedded Die Substrate with Hollow Structure for Heterogeneous Integration

Masamitsu Matsuura, Tanemasa Asano, Haruichi Kanaya

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The residual stress in a silicon die of an embedded die substrate having a hollow structure was investigated. A silicon chip in which piezo-resistance gauges were fabricated was embedded in a hollow chamber inside of the substrate by using a newly developed process technology. The chip was mechanically held with dielectric epoxy resin at the periphery of the chip. Two kinds of the resin having a different coefficient of thermal expansion (CTE) were tested. The residual stress was measured at each critical manufacturing step. The stress was reduced after the formation of the hollow structure. The symmetric structure enabled to minimize the process-induced stress. The use of low CTE resin showed low residual stress.

Original languageEnglish
Title of host publication2020 IEEE 22nd Electronics Packaging Technology Conference, EPTC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages399-402
Number of pages4
ISBN (Electronic)9781728189116
DOIs
Publication statusPublished - Dec 2 2020
Event22nd IEEE Electronics Packaging Technology Conference, EPTC 2020 - Virtual, Singapore, Singapore
Duration: Dec 2 2020Dec 4 2020

Publication series

Name2020 IEEE 22nd Electronics Packaging Technology Conference, EPTC 2020

Conference

Conference22nd IEEE Electronics Packaging Technology Conference, EPTC 2020
Country/TerritorySingapore
CityVirtual, Singapore
Period12/2/2012/4/20

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

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