Evaluation of the scalability of round robin arbiters for NoC routers on FPGA

Maher Abdelrasoul, Mohammed Ragab, Victor Mauro Goulart Ferreira

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

Network-on-Chip (NoC) performance is directly influenced by latency of routers and throughput obtained in some specific topologies. The arbitration inside routers plays an important role in the whole system performance. The size of the arbiters is affected by the node degree and number of virtual channels of the routers. In the literature most of arbiter designs were targeting VLSI, but the mapping of these architectures to the programmable logic and interconnect of an FPGA is not explored. In this paper, we re-evaluate the most famous Round Robin Arbiter (RRA) architectures on FPGA to fulfill this gap. We compare RRA implementations with respect to speed and area. This work will allow NoC designers to scrupulously choose the suitable design of RRA trading-off performance and area.

Original languageEnglish
Title of host publicationProceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013
PublisherIEEE Computer Society
Pages61-64
Number of pages4
ISBN (Print)9780768550862
DOIs
Publication statusPublished - Jan 1 2013
Event2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013 - Tokyo, Japan
Duration: Sep 26 2013Sep 28 2013

Publication series

NameProceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013

Other

Other2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013
CountryJapan
CityTokyo
Period9/26/139/28/13

Fingerprint

Routers
Field programmable gate arrays (FPGA)
Scalability
Throughput
Topology
Network-on-chip

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

Cite this

Abdelrasoul, M., Ragab, M., & Goulart Ferreira, V. M. (2013). Evaluation of the scalability of round robin arbiters for NoC routers on FPGA. In Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013 (pp. 61-64). [6657905] (Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013). IEEE Computer Society. https://doi.org/10.1109/MCSoC.2013.21

Evaluation of the scalability of round robin arbiters for NoC routers on FPGA. / Abdelrasoul, Maher; Ragab, Mohammed; Goulart Ferreira, Victor Mauro.

Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013. IEEE Computer Society, 2013. p. 61-64 6657905 (Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abdelrasoul, M, Ragab, M & Goulart Ferreira, VM 2013, Evaluation of the scalability of round robin arbiters for NoC routers on FPGA. in Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013., 6657905, Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013, IEEE Computer Society, pp. 61-64, 2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013, Tokyo, Japan, 9/26/13. https://doi.org/10.1109/MCSoC.2013.21
Abdelrasoul M, Ragab M, Goulart Ferreira VM. Evaluation of the scalability of round robin arbiters for NoC routers on FPGA. In Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013. IEEE Computer Society. 2013. p. 61-64. 6657905. (Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013). https://doi.org/10.1109/MCSoC.2013.21
Abdelrasoul, Maher ; Ragab, Mohammed ; Goulart Ferreira, Victor Mauro. / Evaluation of the scalability of round robin arbiters for NoC routers on FPGA. Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013. IEEE Computer Society, 2013. pp. 61-64 (Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013).
@inproceedings{fe1f665fd32442ba9cf8ec935892cebc,
title = "Evaluation of the scalability of round robin arbiters for NoC routers on FPGA",
abstract = "Network-on-Chip (NoC) performance is directly influenced by latency of routers and throughput obtained in some specific topologies. The arbitration inside routers plays an important role in the whole system performance. The size of the arbiters is affected by the node degree and number of virtual channels of the routers. In the literature most of arbiter designs were targeting VLSI, but the mapping of these architectures to the programmable logic and interconnect of an FPGA is not explored. In this paper, we re-evaluate the most famous Round Robin Arbiter (RRA) architectures on FPGA to fulfill this gap. We compare RRA implementations with respect to speed and area. This work will allow NoC designers to scrupulously choose the suitable design of RRA trading-off performance and area.",
author = "Maher Abdelrasoul and Mohammed Ragab and {Goulart Ferreira}, {Victor Mauro}",
year = "2013",
month = "1",
day = "1",
doi = "10.1109/MCSoC.2013.21",
language = "English",
isbn = "9780768550862",
series = "Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013",
publisher = "IEEE Computer Society",
pages = "61--64",
booktitle = "Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013",
address = "United States",

}

TY - GEN

T1 - Evaluation of the scalability of round robin arbiters for NoC routers on FPGA

AU - Abdelrasoul, Maher

AU - Ragab, Mohammed

AU - Goulart Ferreira, Victor Mauro

PY - 2013/1/1

Y1 - 2013/1/1

N2 - Network-on-Chip (NoC) performance is directly influenced by latency of routers and throughput obtained in some specific topologies. The arbitration inside routers plays an important role in the whole system performance. The size of the arbiters is affected by the node degree and number of virtual channels of the routers. In the literature most of arbiter designs were targeting VLSI, but the mapping of these architectures to the programmable logic and interconnect of an FPGA is not explored. In this paper, we re-evaluate the most famous Round Robin Arbiter (RRA) architectures on FPGA to fulfill this gap. We compare RRA implementations with respect to speed and area. This work will allow NoC designers to scrupulously choose the suitable design of RRA trading-off performance and area.

AB - Network-on-Chip (NoC) performance is directly influenced by latency of routers and throughput obtained in some specific topologies. The arbitration inside routers plays an important role in the whole system performance. The size of the arbiters is affected by the node degree and number of virtual channels of the routers. In the literature most of arbiter designs were targeting VLSI, but the mapping of these architectures to the programmable logic and interconnect of an FPGA is not explored. In this paper, we re-evaluate the most famous Round Robin Arbiter (RRA) architectures on FPGA to fulfill this gap. We compare RRA implementations with respect to speed and area. This work will allow NoC designers to scrupulously choose the suitable design of RRA trading-off performance and area.

UR - http://www.scopus.com/inward/record.url?scp=84892645388&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84892645388&partnerID=8YFLogxK

U2 - 10.1109/MCSoC.2013.21

DO - 10.1109/MCSoC.2013.21

M3 - Conference contribution

AN - SCOPUS:84892645388

SN - 9780768550862

T3 - Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013

SP - 61

EP - 64

BT - Proceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013

PB - IEEE Computer Society

ER -