Evaluation of the scalability of round robin arbiters for NoC routers on FPGA

Maher Abdelrasoul, Mohammed Ragab, Victor Mauro Goulart Ferreira

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    8 Citations (Scopus)

    Abstract

    Network-on-Chip (NoC) performance is directly influenced by latency of routers and throughput obtained in some specific topologies. The arbitration inside routers plays an important role in the whole system performance. The size of the arbiters is affected by the node degree and number of virtual channels of the routers. In the literature most of arbiter designs were targeting VLSI, but the mapping of these architectures to the programmable logic and interconnect of an FPGA is not explored. In this paper, we re-evaluate the most famous Round Robin Arbiter (RRA) architectures on FPGA to fulfill this gap. We compare RRA implementations with respect to speed and area. This work will allow NoC designers to scrupulously choose the suitable design of RRA trading-off performance and area.

    Original languageEnglish
    Title of host publicationProceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013
    PublisherIEEE Computer Society
    Pages61-64
    Number of pages4
    ISBN (Print)9780768550862
    DOIs
    Publication statusPublished - Jan 1 2013
    Event2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013 - Tokyo, Japan
    Duration: Sep 26 2013Sep 28 2013

    Publication series

    NameProceedings - IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013

    Other

    Other2013 IEEE 7th International Symposium on Embedded Multicore/Manycore System-on-Chip, MCSoC 2013
    Country/TerritoryJapan
    CityTokyo
    Period9/26/139/28/13

    All Science Journal Classification (ASJC) codes

    • Hardware and Architecture

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