TY - GEN
T1 - Examination of residual stress measurement in electronic packages using phase-shifted sampling moiré method and X-ray images
AU - Koganemaru, Masaaki
AU - Uchino, Masakazu
AU - Ikeda, Akihiro
AU - Asano, Tanemasa
N1 - Publisher Copyright:
© 2014 IEEE.
Copyright:
Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2014/11/18
Y1 - 2014/11/18
N2 - This paper examines a novel approach to measure residual stresses in an electronic package. The presented method applies a phase-shifted sampling moiré method to X-ray images of the test chip (Si) in the electronic package. In this study, the test chip including an Au bump grid are made by general semiconductor processes for forming Au bumps on Si chip, and X-ray images of the test chip are taken before and after packaging (resin-molding). Then the phase difference of the sampling moiré fringe patterns before and after packaging can be obtained from the X-ray images of the test chip before and after packaging. The phase difference corresponds to the deformation of the test chip. The results of this examination indicate that the presented method is possible to be used for measuring residual stresses in electronic packages.
AB - This paper examines a novel approach to measure residual stresses in an electronic package. The presented method applies a phase-shifted sampling moiré method to X-ray images of the test chip (Si) in the electronic package. In this study, the test chip including an Au bump grid are made by general semiconductor processes for forming Au bumps on Si chip, and X-ray images of the test chip are taken before and after packaging (resin-molding). Then the phase difference of the sampling moiré fringe patterns before and after packaging can be obtained from the X-ray images of the test chip before and after packaging. The phase difference corresponds to the deformation of the test chip. The results of this examination indicate that the presented method is possible to be used for measuring residual stresses in electronic packages.
UR - http://www.scopus.com/inward/record.url?scp=84918495190&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84918495190&partnerID=8YFLogxK
U2 - 10.1109/ESTC.2014.6962827
DO - 10.1109/ESTC.2014.6962827
M3 - Conference contribution
AN - SCOPUS:84918495190
T3 - Proceedings of the 5th Electronics System-Integration Technology Conference, ESTC 2014
BT - Proceedings of the 5th Electronics System-Integration Technology Conference, ESTC 2014
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 5th Electronics System-Integration Technology Conference, ESTC 2014
Y2 - 16 September 2014 through 18 September 2014
ER -