Fast implementation of Kcipher-2 for software and hardware

Yuto Nakano, Kazuhide Fukushima, Shinsaku Kiyomoto, Tsukasa Ishiguro, Yutaka Miyake, Toshiaki Tanaka, Kouichi Sakurai

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

KCipher-2 is a word-oriented stream cipher and an ISO/IEC 18033 standard. It is listed as a CRYPTREC cryptographic algorithm for Japanese governmental use. It consists of two feedback shift registers and a non-linear function. The size of each register in KCipher-2 is 32 bits and the non-linear function mainly applies 32-bit operations. Therefore, it can be efficiently implemented as software. SNOW-family stream ciphers are also word-oriented stream ciphers, and their high performance has already been demonstrated. We propose optimised implementations of KCipher-2 and compare their performance to that of the SNOW-family and other eSTREAM portfolios. The fastest algorithm is SNOW 2.0 and KCipher-2 is the second fastest despite the complicated irregular clocking mechanism. However, KCipher-2 is the fastest of the feasible algorithms, as SNOW 2.0 has been shown to have a security flaw. We also optimise the hardware implementation for the Virtex-5 field-programmable gate array (FPGA) and show two implementations. The first implementation is a rather straightforward optimisation and achieves 16,153 Mbps with 732 slices. In the second implementation, we duplicate the non-linear function using the structural advantage of KCipher-2 and we achieve 17,354 Mbps with 813 slices. Our implementation of KCipher-2 is around three times faster than those of the SNOW-family and efficiency, which is evaluated by "Throughput/Area (Mbps/slice)", is 3.6-times better than that of SNOW2.0 and 8.5-times better than that of SNOW3G. These syntheses are performed using Xilinx ISE version 12.4.

Original languageEnglish
Pages (from-to)43-52
Number of pages10
JournalIEICE Transactions on Information and Systems
VolumeE97-D
Issue number1
DOIs
Publication statusPublished - Jan 1 2014

Fingerprint

Hardware
Shift registers
Field programmable gate arrays (FPGA)
Throughput
Feedback
Defects

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Artificial Intelligence
  • Electrical and Electronic Engineering

Cite this

Nakano, Y., Fukushima, K., Kiyomoto, S., Ishiguro, T., Miyake, Y., Tanaka, T., & Sakurai, K. (2014). Fast implementation of Kcipher-2 for software and hardware. IEICE Transactions on Information and Systems, E97-D(1), 43-52. https://doi.org/10.1587/transinf.E97.D.43

Fast implementation of Kcipher-2 for software and hardware. / Nakano, Yuto; Fukushima, Kazuhide; Kiyomoto, Shinsaku; Ishiguro, Tsukasa; Miyake, Yutaka; Tanaka, Toshiaki; Sakurai, Kouichi.

In: IEICE Transactions on Information and Systems, Vol. E97-D, No. 1, 01.01.2014, p. 43-52.

Research output: Contribution to journalArticle

Nakano, Y, Fukushima, K, Kiyomoto, S, Ishiguro, T, Miyake, Y, Tanaka, T & Sakurai, K 2014, 'Fast implementation of Kcipher-2 for software and hardware', IEICE Transactions on Information and Systems, vol. E97-D, no. 1, pp. 43-52. https://doi.org/10.1587/transinf.E97.D.43
Nakano Y, Fukushima K, Kiyomoto S, Ishiguro T, Miyake Y, Tanaka T et al. Fast implementation of Kcipher-2 for software and hardware. IEICE Transactions on Information and Systems. 2014 Jan 1;E97-D(1):43-52. https://doi.org/10.1587/transinf.E97.D.43
Nakano, Yuto ; Fukushima, Kazuhide ; Kiyomoto, Shinsaku ; Ishiguro, Tsukasa ; Miyake, Yutaka ; Tanaka, Toshiaki ; Sakurai, Kouichi. / Fast implementation of Kcipher-2 for software and hardware. In: IEICE Transactions on Information and Systems. 2014 ; Vol. E97-D, No. 1. pp. 43-52.
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