TY - GEN

T1 - Fast link-disjoint path algorithm on parallel reconfigurable processor DAPDNA-2

AU - Kihara, Taku

AU - Shimizu, Sho

AU - Arakawa, Yutaka

AU - Yamanaka, Naoaki

AU - Shiba, Kosuke

PY - 2008/12/1

Y1 - 2008/12/1

N2 - This paper proposes fast parallel link-disjoint path algorithm using dynamically reconfigurable processor and implements it on DAPDNA-2 (IPFlex Inc) which is newly structured. The conventional k-shortest path algorithm finds multiple link-disjoint paths between the source node and the destination node. When the network scale is large, the calculation time of k-shortest path algorithm increases rapidly. Moreover, in the worst case, k-shortest path algorithm can not find optimum link-disjoint path pair because this algorithm always finds the shortest path at first and removes those links from network. Our proposed algorithm collects all path information in the network and calculates optimum linkdisjoint path pair (i.e. minimum cost link-disjoint path pair) at high speed by using parallel operation. Additionally, our proposed algorithm finds optimum link-disjoint path pair at a high rate in a limited of calculation time. The evaluation shows our proposed algorithm can decrease the calculation clock about 90%. copyright

AB - This paper proposes fast parallel link-disjoint path algorithm using dynamically reconfigurable processor and implements it on DAPDNA-2 (IPFlex Inc) which is newly structured. The conventional k-shortest path algorithm finds multiple link-disjoint paths between the source node and the destination node. When the network scale is large, the calculation time of k-shortest path algorithm increases rapidly. Moreover, in the worst case, k-shortest path algorithm can not find optimum link-disjoint path pair because this algorithm always finds the shortest path at first and removes those links from network. Our proposed algorithm collects all path information in the network and calculates optimum linkdisjoint path pair (i.e. minimum cost link-disjoint path pair) at high speed by using parallel operation. Additionally, our proposed algorithm finds optimum link-disjoint path pair at a high rate in a limited of calculation time. The evaluation shows our proposed algorithm can decrease the calculation clock about 90%. copyright

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M3 - Conference contribution

AN - SCOPUS:66149153350

SN - 4885522323

SN - 9784885522321

T3 - 2008 14th Asia-Pacific Conference on Communications, APCC 2008

BT - 2008 14th Asia-Pacific Conference on Communications, APCC 2008

T2 - 2008 14th Asia-Pacific Conference on Communications, APCC 2008

Y2 - 14 October 2008 through 16 October 2008

ER -