Fast link-disjoint path algorithm on parallel reconfigurable processor DAPDNA-2

Taku Kihara, Sho Shimizu, Yutaka Arakawa, Naoaki Yamanaka, Kosuke Shiba

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper proposes fast parallel link-disjoint path algorithm using dynamically reconfigurable processor and implements it on DAPDNA-2 (IPFlex Inc) which is newly structured. The conventional k-shortest path algorithm finds multiple link-disjoint paths between the source node and the destination node. When the network scale is large, the calculation time of k-shortest path algorithm increases rapidly. Moreover, in the worst case, k-shortest path algorithm can not find optimum link-disjoint path pair because this algorithm always finds the shortest path at first and removes those links from network. Our proposed algorithm collects all path information in the network and calculates optimum linkdisjoint path pair (i.e. minimum cost link-disjoint path pair) at high speed by using parallel operation. Additionally, our proposed algorithm finds optimum link-disjoint path pair at a high rate in a limited of calculation time. The evaluation shows our proposed algorithm can decrease the calculation clock about 90%. copyright

Original languageEnglish
Title of host publication2008 14th Asia-Pacific Conference on Communications, APCC 2008
Publication statusPublished - Dec 1 2008
Externally publishedYes
Event2008 14th Asia-Pacific Conference on Communications, APCC 2008 - Akihabara, Tokyo, United States
Duration: Oct 14 2008Oct 16 2008

Publication series

Name2008 14th Asia-Pacific Conference on Communications, APCC 2008

Other

Other2008 14th Asia-Pacific Conference on Communications, APCC 2008
CountryUnited States
CityAkihabara, Tokyo
Period10/14/0810/16/08

Fingerprint

Clocks
costs
evaluation
Costs
time

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Communication

Cite this

Kihara, T., Shimizu, S., Arakawa, Y., Yamanaka, N., & Shiba, K. (2008). Fast link-disjoint path algorithm on parallel reconfigurable processor DAPDNA-2. In 2008 14th Asia-Pacific Conference on Communications, APCC 2008 [4773784] (2008 14th Asia-Pacific Conference on Communications, APCC 2008).

Fast link-disjoint path algorithm on parallel reconfigurable processor DAPDNA-2. / Kihara, Taku; Shimizu, Sho; Arakawa, Yutaka; Yamanaka, Naoaki; Shiba, Kosuke.

2008 14th Asia-Pacific Conference on Communications, APCC 2008. 2008. 4773784 (2008 14th Asia-Pacific Conference on Communications, APCC 2008).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Kihara, T, Shimizu, S, Arakawa, Y, Yamanaka, N & Shiba, K 2008, Fast link-disjoint path algorithm on parallel reconfigurable processor DAPDNA-2. in 2008 14th Asia-Pacific Conference on Communications, APCC 2008., 4773784, 2008 14th Asia-Pacific Conference on Communications, APCC 2008, 2008 14th Asia-Pacific Conference on Communications, APCC 2008, Akihabara, Tokyo, United States, 10/14/08.
Kihara T, Shimizu S, Arakawa Y, Yamanaka N, Shiba K. Fast link-disjoint path algorithm on parallel reconfigurable processor DAPDNA-2. In 2008 14th Asia-Pacific Conference on Communications, APCC 2008. 2008. 4773784. (2008 14th Asia-Pacific Conference on Communications, APCC 2008).
Kihara, Taku ; Shimizu, Sho ; Arakawa, Yutaka ; Yamanaka, Naoaki ; Shiba, Kosuke. / Fast link-disjoint path algorithm on parallel reconfigurable processor DAPDNA-2. 2008 14th Asia-Pacific Conference on Communications, APCC 2008. 2008. (2008 14th Asia-Pacific Conference on Communications, APCC 2008).
@inproceedings{3df31ccd593a419087751bc77f69f609,
title = "Fast link-disjoint path algorithm on parallel reconfigurable processor DAPDNA-2",
abstract = "This paper proposes fast parallel link-disjoint path algorithm using dynamically reconfigurable processor and implements it on DAPDNA-2 (IPFlex Inc) which is newly structured. The conventional k-shortest path algorithm finds multiple link-disjoint paths between the source node and the destination node. When the network scale is large, the calculation time of k-shortest path algorithm increases rapidly. Moreover, in the worst case, k-shortest path algorithm can not find optimum link-disjoint path pair because this algorithm always finds the shortest path at first and removes those links from network. Our proposed algorithm collects all path information in the network and calculates optimum linkdisjoint path pair (i.e. minimum cost link-disjoint path pair) at high speed by using parallel operation. Additionally, our proposed algorithm finds optimum link-disjoint path pair at a high rate in a limited of calculation time. The evaluation shows our proposed algorithm can decrease the calculation clock about 90{\%}. copyright",
author = "Taku Kihara and Sho Shimizu and Yutaka Arakawa and Naoaki Yamanaka and Kosuke Shiba",
year = "2008",
month = "12",
day = "1",
language = "English",
isbn = "4885522323",
series = "2008 14th Asia-Pacific Conference on Communications, APCC 2008",
booktitle = "2008 14th Asia-Pacific Conference on Communications, APCC 2008",

}

TY - GEN

T1 - Fast link-disjoint path algorithm on parallel reconfigurable processor DAPDNA-2

AU - Kihara, Taku

AU - Shimizu, Sho

AU - Arakawa, Yutaka

AU - Yamanaka, Naoaki

AU - Shiba, Kosuke

PY - 2008/12/1

Y1 - 2008/12/1

N2 - This paper proposes fast parallel link-disjoint path algorithm using dynamically reconfigurable processor and implements it on DAPDNA-2 (IPFlex Inc) which is newly structured. The conventional k-shortest path algorithm finds multiple link-disjoint paths between the source node and the destination node. When the network scale is large, the calculation time of k-shortest path algorithm increases rapidly. Moreover, in the worst case, k-shortest path algorithm can not find optimum link-disjoint path pair because this algorithm always finds the shortest path at first and removes those links from network. Our proposed algorithm collects all path information in the network and calculates optimum linkdisjoint path pair (i.e. minimum cost link-disjoint path pair) at high speed by using parallel operation. Additionally, our proposed algorithm finds optimum link-disjoint path pair at a high rate in a limited of calculation time. The evaluation shows our proposed algorithm can decrease the calculation clock about 90%. copyright

AB - This paper proposes fast parallel link-disjoint path algorithm using dynamically reconfigurable processor and implements it on DAPDNA-2 (IPFlex Inc) which is newly structured. The conventional k-shortest path algorithm finds multiple link-disjoint paths between the source node and the destination node. When the network scale is large, the calculation time of k-shortest path algorithm increases rapidly. Moreover, in the worst case, k-shortest path algorithm can not find optimum link-disjoint path pair because this algorithm always finds the shortest path at first and removes those links from network. Our proposed algorithm collects all path information in the network and calculates optimum linkdisjoint path pair (i.e. minimum cost link-disjoint path pair) at high speed by using parallel operation. Additionally, our proposed algorithm finds optimum link-disjoint path pair at a high rate in a limited of calculation time. The evaluation shows our proposed algorithm can decrease the calculation clock about 90%. copyright

UR - http://www.scopus.com/inward/record.url?scp=66149153350&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=66149153350&partnerID=8YFLogxK

M3 - Conference contribution

SN - 4885522323

SN - 9784885522321

T3 - 2008 14th Asia-Pacific Conference on Communications, APCC 2008

BT - 2008 14th Asia-Pacific Conference on Communications, APCC 2008

ER -