Fast state reduction algorithm for incompletely specified finite state machines

Hiroyuki Higuchi, Yusuke Matsunaga

Research output: Contribution to journalConference article

11 Citations (Scopus)

Abstract

This paper proposes a state reduction algorithm for incompletely specified FSMs. The algorithm is based on iterative improvements. When the number of compatibles is likely to be too large to handle explicitly, they are represented by a BDD. Experimental results are given to demonstrate that the algorithm described here is faster and obtains better solutions than conventional methods.

Original languageEnglish
Pages (from-to)463-466
Number of pages4
JournalProceedings - Design Automation Conference
Publication statusPublished - Jan 1 1996
EventProceedings of the 1996 33rd Annual Design Automation Conference - Las Vegas, NV, USA
Duration: Jun 3 1996Jun 7 1996

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Finite automata

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

Cite this

Fast state reduction algorithm for incompletely specified finite state machines. / Higuchi, Hiroyuki; Matsunaga, Yusuke.

In: Proceedings - Design Automation Conference, 01.01.1996, p. 463-466.

Research output: Contribution to journalConference article

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