### Abstract

This paper proposes a technique of functional information extraction which transforms design description at the logic circuit level in the LSI design process to a description at functional level. This technology is considered to be a powerful means of logic design verification similar to the circuit extraction technology already in practical use for layout design verification. Moreover, by automatically generating function description language from given circuit description, it can be used in functional and fault simulations and is useful in reusing circuits. An extraction technique of logic and arithmetic functions of combinational circuits is investigated herein. As internal representation of logic functions, binary decision diagrams are used for efficient treatment. For extraction of arithmetic functions, a technique of first extracting logic functions, and then representing them by arithmetic expressions is used. This technique has a characteristic that the same function description is obtained from circuits with the same functions even though their circuit structures are different. Therefore, functional information extraction independent of circuit structure can be done. This paper describes first the extraction of logic functions, which is the basic technique, and then explains the arithmetic function extraction technique. Finally, some concrete examples are evaluated.

Original language | English |
---|---|

Pages (from-to) | 28-38 |

Number of pages | 11 |

Journal | Electronics and Communications in Japan (Part III: Fundamental Electronic Science) |

Volume | 74 |

Issue number | 11 |

DOIs | |

Publication status | Published - Jan 1 1991 |

Externally published | Yes |

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### All Science Journal Classification (ASJC) codes

- Electrical and Electronic Engineering

### Cite this

*Electronics and Communications in Japan (Part III: Fundamental Electronic Science)*,

*74*(11), 28-38. https://doi.org/10.1002/ecjc.4430741103

**Functional information extraction from combinational circuits.** / Ohmura, Masahiko; Yasuura, Hiroto; Tamaru, Keikichi.

Research output: Contribution to journal › Article

*Electronics and Communications in Japan (Part III: Fundamental Electronic Science)*, vol. 74, no. 11, pp. 28-38. https://doi.org/10.1002/ecjc.4430741103

}

TY - JOUR

T1 - Functional information extraction from combinational circuits

AU - Ohmura, Masahiko

AU - Yasuura, Hiroto

AU - Tamaru, Keikichi

PY - 1991/1/1

Y1 - 1991/1/1

N2 - This paper proposes a technique of functional information extraction which transforms design description at the logic circuit level in the LSI design process to a description at functional level. This technology is considered to be a powerful means of logic design verification similar to the circuit extraction technology already in practical use for layout design verification. Moreover, by automatically generating function description language from given circuit description, it can be used in functional and fault simulations and is useful in reusing circuits. An extraction technique of logic and arithmetic functions of combinational circuits is investigated herein. As internal representation of logic functions, binary decision diagrams are used for efficient treatment. For extraction of arithmetic functions, a technique of first extracting logic functions, and then representing them by arithmetic expressions is used. This technique has a characteristic that the same function description is obtained from circuits with the same functions even though their circuit structures are different. Therefore, functional information extraction independent of circuit structure can be done. This paper describes first the extraction of logic functions, which is the basic technique, and then explains the arithmetic function extraction technique. Finally, some concrete examples are evaluated.

AB - This paper proposes a technique of functional information extraction which transforms design description at the logic circuit level in the LSI design process to a description at functional level. This technology is considered to be a powerful means of logic design verification similar to the circuit extraction technology already in practical use for layout design verification. Moreover, by automatically generating function description language from given circuit description, it can be used in functional and fault simulations and is useful in reusing circuits. An extraction technique of logic and arithmetic functions of combinational circuits is investigated herein. As internal representation of logic functions, binary decision diagrams are used for efficient treatment. For extraction of arithmetic functions, a technique of first extracting logic functions, and then representing them by arithmetic expressions is used. This technique has a characteristic that the same function description is obtained from circuits with the same functions even though their circuit structures are different. Therefore, functional information extraction independent of circuit structure can be done. This paper describes first the extraction of logic functions, which is the basic technique, and then explains the arithmetic function extraction technique. Finally, some concrete examples are evaluated.

UR - http://www.scopus.com/inward/record.url?scp=0026259455&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026259455&partnerID=8YFLogxK

U2 - 10.1002/ecjc.4430741103

DO - 10.1002/ecjc.4430741103

M3 - Article

AN - SCOPUS:0026259455

VL - 74

SP - 28

EP - 38

JO - Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)

JF - Electronics and Communications in Japan, Part III: Fundamental Electronic Science (English translation of Denshi Tsushin Gakkai Ronbunshi)

SN - 1042-0967

IS - 11

ER -