Gate drive circuit for current balancing of parallel-connected SiC-JFETs under avalanche mode

Taro Takamori, Keiji Wada, Wataru Saito, Shin ichi Nishizawa

Research output: Contribution to journalArticlepeer-review

Abstract

This paper proposes a gate drive circuit for the current balancing of parallel-connected SiC-JFETs under avalanche mode. For a solid-state DC circuit breaker, the power devices have to be connected in parallel to reduce the ON-resistance and increase the current rating. In addition, it is reported that the SiC-JFET is suitable power devices from the viewpoint of both conduction loss and long-term reliability. This paper presents the behavior of current balancing of SiC-JFETs in parallel, and then proposes a design procedure of gate drive circuits. The gate drive circuits can achieve the current balance equalization of parallel-connected SiC-JFETs under avalanche mode. The validity of the proposed gate drive circuit is verified by the experiment that uses 1.2 kV SiC-JFETs in a 400 V system.

Original languageEnglish
Article number113776
JournalMicroelectronics Reliability
Volume114
DOIs
Publication statusPublished - Nov 2020

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Safety, Risk, Reliability and Quality
  • Condensed Matter Physics
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

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