TY - JOUR
T1 - Ge field-effect transistor with asymmetric metal source/drain fabricated on Ge-on-Insulator
T2 - Schottky tunneling source mode operation and conventional mode operation
AU - Yamamoto, Keisuke
AU - Nakae, Kohei
AU - Wang, Dong
AU - Nakashima, Hiroshi
AU - Xue, Zhongying
AU - Zhang, Miao
AU - Di, Zengfeng
N1 - Publisher Copyright:
© 2019 The Japan Society of Applied Physics.
PY - 2019
Y1 - 2019
N2 - An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short-channel effect. Recently, we succeeded in the fabrication and operation of a Ge-STS n-channel FET with TiN and PtGe asymmetric metal source/drain (S/D) on a bulk Ge substrate. However, the Ge-STS p-channel FET has not been demonstrated yet. In this study, we fabricated an asymmetric metal S/D FET with the same S/D structure on a bulk Ge and a Ge-on-Insulator (GOI) substrate. The GOI was made by using the Smart-CutTM technique. The device fabricated on a bulk Ge did not operate. On the other hand, the fabricated FET on a GOI, which has a taper-shaped TiN/Ge source interface, showed STS p-FET behavior. These results suggest that the carrier injection can be improved by the optimization of the device structure. As an auxiliary effect, conventional metal-oxide-semiconductor (MOS) FET operation was also observed, thanks to GOI introduction. We demonstrated both STS mode and MOSFET mode operation in the same device on GOI.
AB - An asymmetric Schottky tunneling source field-effect transistor (STS FET) is a prospective device structure to suppress the short-channel effect. Recently, we succeeded in the fabrication and operation of a Ge-STS n-channel FET with TiN and PtGe asymmetric metal source/drain (S/D) on a bulk Ge substrate. However, the Ge-STS p-channel FET has not been demonstrated yet. In this study, we fabricated an asymmetric metal S/D FET with the same S/D structure on a bulk Ge and a Ge-on-Insulator (GOI) substrate. The GOI was made by using the Smart-CutTM technique. The device fabricated on a bulk Ge did not operate. On the other hand, the fabricated FET on a GOI, which has a taper-shaped TiN/Ge source interface, showed STS p-FET behavior. These results suggest that the carrier injection can be improved by the optimization of the device structure. As an auxiliary effect, conventional metal-oxide-semiconductor (MOS) FET operation was also observed, thanks to GOI introduction. We demonstrated both STS mode and MOSFET mode operation in the same device on GOI.
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U2 - 10.7567/1347-4065/ab02e3
DO - 10.7567/1347-4065/ab02e3
M3 - Article
AN - SCOPUS:85065496536
SN - 0021-4922
VL - 58
JO - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
JF - Japanese Journal of Applied Physics, Part 1: Regular Papers & Short Notes
IS - SB
M1 - SBBA14
ER -