Grain positioning using metal imprint technology for single-grain Si thin-film transistor

Kenji Makihira, Masahito Yoshii, Tanemasa Asano

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

We prepared a large-grain silicon thin film by a new solid-phase crystallization technology called metal imprint technology, fabricated a prototype of a quasi-single-crystal silicon (Si) thin-film transistor (TFT), and evaluated its performance. Metal imprint technology presses a chip array coated by metal onto amorphous silicon and promotes the nucleation in solid-phase crystallization by the metal transferred to a small area. By using nickel (Ni) in the imprinting, we found that the incubation time could be significantly decreased, and large grains could be formed at any desired positions. The grains we obtained had a 〈111〉 orientation. An average 7-μm grain size was obtained by annealing at 560 °C. This technology was used to fabricate TFT that positioned the channel region in a single grain. The fabricated TFT exhibited excellent performance in the field effect mobilities of 400 cm2/Vs in the n-channel and 220 cm2/Vs in the p-channel. We found that dispersion in mobility of TFTs could be reduced to one-half of the dispersion of polycrystalline-Si TFT that was crystallized in the conventional solid phase. Threshold voltages had excellent uniformity and were about one-half of those of a conventional solid-phase crystallized TFT.

Original languageEnglish
Pages (from-to)45-51
Number of pages7
JournalElectronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)
Volume86
Issue number5
DOIs
Publication statusPublished - May 2003
Externally publishedYes

Fingerprint

Thin film transistors
positioning
transistors
Silicon
solid phases
silicon
thin films
Metals
metals
Crystallization
crystallization
Amorphous silicon
Threshold voltage
Polysilicon
Nucleation
threshold voltage
amorphous silicon
Nickel
Single crystals
Annealing

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

Grain positioning using metal imprint technology for single-grain Si thin-film transistor. / Makihira, Kenji; Yoshii, Masahito; Asano, Tanemasa.

In: Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi), Vol. 86, No. 5, 05.2003, p. 45-51.

Research output: Contribution to journalArticle

@article{e2c26dbf9f1b483db55ba69081bdccb1,
title = "Grain positioning using metal imprint technology for single-grain Si thin-film transistor",
abstract = "We prepared a large-grain silicon thin film by a new solid-phase crystallization technology called metal imprint technology, fabricated a prototype of a quasi-single-crystal silicon (Si) thin-film transistor (TFT), and evaluated its performance. Metal imprint technology presses a chip array coated by metal onto amorphous silicon and promotes the nucleation in solid-phase crystallization by the metal transferred to a small area. By using nickel (Ni) in the imprinting, we found that the incubation time could be significantly decreased, and large grains could be formed at any desired positions. The grains we obtained had a 〈111〉 orientation. An average 7-μm grain size was obtained by annealing at 560 °C. This technology was used to fabricate TFT that positioned the channel region in a single grain. The fabricated TFT exhibited excellent performance in the field effect mobilities of 400 cm2/Vs in the n-channel and 220 cm2/Vs in the p-channel. We found that dispersion in mobility of TFTs could be reduced to one-half of the dispersion of polycrystalline-Si TFT that was crystallized in the conventional solid phase. Threshold voltages had excellent uniformity and were about one-half of those of a conventional solid-phase crystallized TFT.",
author = "Kenji Makihira and Masahito Yoshii and Tanemasa Asano",
year = "2003",
month = "5",
doi = "10.1002/ecjb.10099",
language = "English",
volume = "86",
pages = "45--51",
journal = "Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)",
issn = "8756-663X",
publisher = "Scripta Technica",
number = "5",

}

TY - JOUR

T1 - Grain positioning using metal imprint technology for single-grain Si thin-film transistor

AU - Makihira, Kenji

AU - Yoshii, Masahito

AU - Asano, Tanemasa

PY - 2003/5

Y1 - 2003/5

N2 - We prepared a large-grain silicon thin film by a new solid-phase crystallization technology called metal imprint technology, fabricated a prototype of a quasi-single-crystal silicon (Si) thin-film transistor (TFT), and evaluated its performance. Metal imprint technology presses a chip array coated by metal onto amorphous silicon and promotes the nucleation in solid-phase crystallization by the metal transferred to a small area. By using nickel (Ni) in the imprinting, we found that the incubation time could be significantly decreased, and large grains could be formed at any desired positions. The grains we obtained had a 〈111〉 orientation. An average 7-μm grain size was obtained by annealing at 560 °C. This technology was used to fabricate TFT that positioned the channel region in a single grain. The fabricated TFT exhibited excellent performance in the field effect mobilities of 400 cm2/Vs in the n-channel and 220 cm2/Vs in the p-channel. We found that dispersion in mobility of TFTs could be reduced to one-half of the dispersion of polycrystalline-Si TFT that was crystallized in the conventional solid phase. Threshold voltages had excellent uniformity and were about one-half of those of a conventional solid-phase crystallized TFT.

AB - We prepared a large-grain silicon thin film by a new solid-phase crystallization technology called metal imprint technology, fabricated a prototype of a quasi-single-crystal silicon (Si) thin-film transistor (TFT), and evaluated its performance. Metal imprint technology presses a chip array coated by metal onto amorphous silicon and promotes the nucleation in solid-phase crystallization by the metal transferred to a small area. By using nickel (Ni) in the imprinting, we found that the incubation time could be significantly decreased, and large grains could be formed at any desired positions. The grains we obtained had a 〈111〉 orientation. An average 7-μm grain size was obtained by annealing at 560 °C. This technology was used to fabricate TFT that positioned the channel region in a single grain. The fabricated TFT exhibited excellent performance in the field effect mobilities of 400 cm2/Vs in the n-channel and 220 cm2/Vs in the p-channel. We found that dispersion in mobility of TFTs could be reduced to one-half of the dispersion of polycrystalline-Si TFT that was crystallized in the conventional solid phase. Threshold voltages had excellent uniformity and were about one-half of those of a conventional solid-phase crystallized TFT.

UR - http://www.scopus.com/inward/record.url?scp=0038733757&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0038733757&partnerID=8YFLogxK

U2 - 10.1002/ecjb.10099

DO - 10.1002/ecjb.10099

M3 - Article

VL - 86

SP - 45

EP - 51

JO - Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)

JF - Electronics and Communications in Japan, Part II: Electronics (English translation of Denshi Tsushin Gakkai Ronbunshi)

SN - 8756-663X

IS - 5

ER -