TY - GEN
T1 - Hardware and software requirements for implementing a high-performance superconductivity circuits-based accelerator
AU - Mehdipour, Farhad
AU - Honda, Hiroaki
AU - Inoue, Koji
AU - Murakami, Kazuaki
PY - 2011/12/1
Y1 - 2011/12/1
N2 - Single-Flux Quantum based large-scale data-path processor (SFQ-LSRDP) is a reconfigurable computing system which is implemented by means of superconductivity circuits. SFQ-LSRDP has a capability of accelerating data flow graphs (DFGs) extracted from scientific applications. Using an alternative technology instead of CMOS circuits for implementing such hardware entails considering particular constraints and conditions from the architecture and tools development perspectives. In this paper, we will introduce hardware specifications of the LSRDP and the tool chain developed for implementing applications. Placing and routing data flow graphs is a fundamental part to develop applications on the SFQ-LSRDP. Algorithms for placing DFG operations and routing nets corresponding to the edges of data flow graphs will be discussed in more details. These algorithms have been applied on a number of data flow graphs and the results demonstrate their efficiency. Further, simulation results demonstrates remarkable performance numbers in the range of hundreds of Gflops for the proposed architecture.
AB - Single-Flux Quantum based large-scale data-path processor (SFQ-LSRDP) is a reconfigurable computing system which is implemented by means of superconductivity circuits. SFQ-LSRDP has a capability of accelerating data flow graphs (DFGs) extracted from scientific applications. Using an alternative technology instead of CMOS circuits for implementing such hardware entails considering particular constraints and conditions from the architecture and tools development perspectives. In this paper, we will introduce hardware specifications of the LSRDP and the tool chain developed for implementing applications. Placing and routing data flow graphs is a fundamental part to develop applications on the SFQ-LSRDP. Algorithms for placing DFG operations and routing nets corresponding to the edges of data flow graphs will be discussed in more details. These algorithms have been applied on a number of data flow graphs and the results demonstrate their efficiency. Further, simulation results demonstrates remarkable performance numbers in the range of hundreds of Gflops for the proposed architecture.
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U2 - 10.1109/ASQED.2011.6111751
DO - 10.1109/ASQED.2011.6111751
M3 - Conference contribution
AN - SCOPUS:84855896754
SN - 9781457701443
T3 - Proceedings of the 3rd Asia Symposium on Quality Electronic Design, ASQED 2011
SP - 229
EP - 235
BT - Proceedings of the 3rd Asia Symposium on Quality Electronic Design, ASQED 2011
ER -