Hardware based scalable path computation engine for multilayer traffic engineering in GMPLS networks

Shimizu Sho, Kihara Taku, Yutaka Arakawa, Yamanaka Naoaki, Shiba Kosuke

Research output: Contribution to conferencePaperpeer-review

Abstract

A parallel data-flow hardware based path computation engine that makes multilayer traffic engineering more scalable is proposed. The engine achieves 100 times faster than conventional path computation scheme.

Original languageEnglish
DOIs
Publication statusPublished - Dec 1 2008
Externally publishedYes
Event2008 34th European Conference on Optical Communication, ECOC 2008 - Brussels, Belgium
Duration: Sep 21 2008Sep 25 2008

Other

Other2008 34th European Conference on Optical Communication, ECOC 2008
CountryBelgium
CityBrussels
Period9/21/089/25/08

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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