HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.

Kei Suzuki; Yusuke Matsunaga; Masayoshi Tachibana; Tatsuo Ohtsuki

HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.

Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki

Research output: Contribution to journal › Article › peer-review

Abstract

A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

Original language	English
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	CAD-5
Issue number	4
Publication status	Published - Oct 1986
Externally published	Yes

All Science Journal Classification (ASJC) codes

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Cite this

@article{bc4ff1103d68463b942a17489d9a3d8e,

title = "HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.",

abstract = "A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.",

author = "Kei Suzuki and Yusuke Matsunaga and Masayoshi Tachibana and Tatsuo Ohtsuki",

note = "Funding Information: We would like to extend our thanks to H. Satake for her technical assistance, and K. Ujiie for her secretarial assistance. This work was supported in part by Grant-in-Aid for Scientific Research on Priority areas “Cancer”, from the Ministry of Education, Science, Sports and Culture of Japan.",

year = "1986",

month = oct,

language = "English",

volume = "CAD-5",

journal = "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems",

issn = "0278-0070",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "4",

}

TY - JOUR

T1 - HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.

AU - Suzuki, Kei

AU - Matsunaga, Yusuke

AU - Tachibana, Masayoshi

AU - Ohtsuki, Tatsuo

N1 - Funding Information: We would like to extend our thanks to H. Satake for her technical assistance, and K. Ujiie for her secretarial assistance. This work was supported in part by Grant-in-Aid for Scientific Research on Priority areas “Cancer”, from the Ministry of Education, Science, Sports and Culture of Japan.

PY - 1986/10

Y1 - 1986/10

N2 - A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

AB - A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

UR - http://www.scopus.com/inward/record.url?scp=0022795581&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0022795581&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:0022795581

SN - 0278-0070

VL - CAD-5

JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

IS - 4

ER -

HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.

Abstract

All Science Journal Classification (ASJC) codes

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