TY - JOUR
T1 - HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.
AU - Suzuki, Kei
AU - Matsunaga, Yusuke
AU - Tachibana, Masayoshi
AU - Ohtsuki, Tatsuo
N1 - Funding Information:
We would like to extend our thanks to H. Satake for her technical assistance, and K. Ujiie for her secretarial assistance. This work was supported in part by Grant-in-Aid for Scientific Research on Priority areas “Cancer”, from the Ministry of Education, Science, Sports and Culture of Japan.
PY - 1986/10
Y1 - 1986/10
N2 - A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.
AB - A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.
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M3 - Article
AN - SCOPUS:0022795581
SN - 0278-0070
VL - CAD-5
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IS - 4
ER -