HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.

Kei Suzuki; Yusuke Matsunaga; Masayoshi Tachibana; Tatsuo Ohtsuki

HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.

Kei Suzuki, Yusuke Matsunaga, Masayoshi Tachibana, Tatsuo Ohtsuki

Research output: Contribution to journal › Article › peer-review

Abstract

A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

Original language	English
Journal	IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume	CAD-5
Issue number	4
Publication status	Published - Oct 1 1986
Externally published	Yes

All Science Journal Classification (ASJC) codes

Software
Computer Graphics and Computer-Aided Design
Electrical and Electronic Engineering

Cite this

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abstract = "A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.",

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AU - Ohtsuki, Tatsuo

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AB - A parallel-processing architecture for hardware routers based on the Lee algorithm is presented. Unlike the existing machines, which require N**2 processors to implement the Lee algorithm on an N multiplied by N grid plane, the proposed architecture requires only O(N) processors to find a path in O(N) time. A prototype machine with 64 processors has been developed to deal with a 128 multiplied by 128 grid plane. The architecture of the machine is discussed, together with its experimental performance data. The parallel processed Lee algorithm is most useful and powerful when applied to interactive rip-up and reroute.

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ER -

HARDWARE MAZE ROUTER WITH APPLICATION TO INTERACTIVE RIP-UP AND REROUTE.

Abstract

All Science Journal Classification (ASJC) codes

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