Heterogeneous multiprocessor synthesis under performance and reliability constraints

Makoto Sugihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to single event upsets (SEUs), has not been taken into account in a conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and reliability constraints. First we define an SEU vulnerability factor for computer systems so that we evaluate reliability of a task over various processor configurations. Next we build a mixed integer linear programming (MILP) model for minimizing chip area of a heterogeneous multiprocessor system under real-time and SEU vulnerability constraints. Finally, we show several experimental results on our synthesis approach. Experimental results show that our design paradigm has achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.

Original languageEnglish
Title of host publication12th Euromicro Conference on Digital System Design
Subtitle of host publicationArchitectures, Methods and Tools, DSD 2009
Pages333-340
Number of pages8
DOIs
Publication statusPublished - Dec 1 2009
Event12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009 - Patras, Greece
Duration: Aug 27 2009Aug 29 2009

Other

Other12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009
CountryGreece
CityPatras
Period8/27/098/29/09

Fingerprint

Embedded systems
Linear programming
Costs
Computer systems
Electric power utilization
Systems analysis
Integrated circuit design

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Cite this

Sugihara, M. (2009). Heterogeneous multiprocessor synthesis under performance and reliability constraints. In 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009 (pp. 333-340). [5350058] https://doi.org/10.1109/DSD.2009.217

Heterogeneous multiprocessor synthesis under performance and reliability constraints. / Sugihara, Makoto.

12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009. 2009. p. 333-340 5350058.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sugihara, M 2009, Heterogeneous multiprocessor synthesis under performance and reliability constraints. in 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009., 5350058, pp. 333-340, 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009, Patras, Greece, 8/27/09. https://doi.org/10.1109/DSD.2009.217
Sugihara M. Heterogeneous multiprocessor synthesis under performance and reliability constraints. In 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009. 2009. p. 333-340. 5350058 https://doi.org/10.1109/DSD.2009.217
Sugihara, Makoto. / Heterogeneous multiprocessor synthesis under performance and reliability constraints. 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009. 2009. pp. 333-340
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