Heterogeneous multiprocessor synthesis under performance and reliability constraints

Makoto Sugihara

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to single event upsets (SEUs), has not been taken into account in a conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and reliability constraints. First we define an SEU vulnerability factor for computer systems so that we evaluate reliability of a task over various processor configurations. Next we build a mixed integer linear programming (MILP) model for minimizing chip area of a heterogeneous multiprocessor system under real-time and SEU vulnerability constraints. Finally, we show several experimental results on our synthesis approach. Experimental results show that our design paradigm has achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.

Original languageEnglish
Title of host publication12th Euromicro Conference on Digital System Design
Subtitle of host publicationArchitectures, Methods and Tools, DSD 2009
Pages333-340
Number of pages8
DOIs
Publication statusPublished - Dec 1 2009
Event12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009 - Patras, Greece
Duration: Aug 27 2009Aug 29 2009

Other

Other12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009
CountryGreece
CityPatras
Period8/27/098/29/09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Software
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Heterogeneous multiprocessor synthesis under performance and reliability constraints'. Together they form a unique fingerprint.

Cite this