Abstract
Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to single event upsets (SEUs), has not been taken into account in a conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and reliability constraints. First we define an SEU vulnerability factor for computer systems so that we evaluate reliability of a task over various processor configurations. Next we build a mixed integer linear programming (MILP) model for minimizing chip area of a heterogeneous multiprocessor system under real-time and SEU vulnerability constraints. Finally, we show several experimental results on our synthesis approach. Experimental results show that our design paradigm has achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.
| Original language | English |
|---|---|
| Title of host publication | 12th Euromicro Conference on Digital System Design |
| Subtitle of host publication | Architectures, Methods and Tools, DSD 2009 |
| Pages | 333-340 |
| Number of pages | 8 |
| DOIs | |
| Publication status | Published - Dec 1 2009 |
| Event | 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009 - Patras, Greece Duration: Aug 27 2009 → Aug 29 2009 |
Other
| Other | 12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009 |
|---|---|
| Country | Greece |
| City | Patras |
| Period | 8/27/09 → 8/29/09 |
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All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Software
- Electrical and Electronic Engineering
Cite this
Heterogeneous multiprocessor synthesis under performance and reliability constraints. / Sugihara, Makoto.
12th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2009. 2009. p. 333-340 5350058.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - Heterogeneous multiprocessor synthesis under performance and reliability constraints
AU - Sugihara, Makoto
PY - 2009/12/1
Y1 - 2009/12/1
N2 - Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to single event upsets (SEUs), has not been taken into account in a conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and reliability constraints. First we define an SEU vulnerability factor for computer systems so that we evaluate reliability of a task over various processor configurations. Next we build a mixed integer linear programming (MILP) model for minimizing chip area of a heterogeneous multiprocessor system under real-time and SEU vulnerability constraints. Finally, we show several experimental results on our synthesis approach. Experimental results show that our design paradigm has achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.
AB - Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost. A reliability issue, which is vulnerability to single event upsets (SEUs), has not been taken into account in a conventional IC (integrated circuit) design flow, while chip area, performance, and power consumption have been done. This paper presents a system design paradigm in which a heterogeneous multiprocessor system is synthesized and its chip area is minimized under real-time and reliability constraints. First we define an SEU vulnerability factor for computer systems so that we evaluate reliability of a task over various processor configurations. Next we build a mixed integer linear programming (MILP) model for minimizing chip area of a heterogeneous multiprocessor system under real-time and SEU vulnerability constraints. Finally, we show several experimental results on our synthesis approach. Experimental results show that our design paradigm has achieved automatic generation of cost-competitive and reliable heterogeneous multiprocessor systems.
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UR - http://www.scopus.com/inward/citedby.url?scp=74749091584&partnerID=8YFLogxK
U2 - 10.1109/DSD.2009.217
DO - 10.1109/DSD.2009.217
M3 - Conference contribution
AN - SCOPUS:74749091584
SN - 9780769537825
SP - 333
EP - 340
BT - 12th Euromicro Conference on Digital System Design
ER -