Hierarchical intellectual property protection using partially-mergeable cores

Vikram Iyengar, Hiroshi Date, Makoto Sugihara, Krishnendu Chakrabarty

Research output: Contribution to journalArticle

Abstract

We present a new technique for hierarchical intellectual property (IP) protection using partially-mergeable cores. The proposed core partitioning technique guarantees 100% protection of critical-IP, while simplifying test generation for the logic that is merged with the system. Since critical-IP is tested using BIST, the controllability and observability of internal lines in the core are enhanced, and test application time is reduced. Case studies using the ISIT-DLX and Picojava processor cores demonstrate the applicability of our technique.

Original languageEnglish
Pages (from-to)2632-2638
Number of pages7
JournalIEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
VolumeE84-A
Issue number11
Publication statusPublished - Jan 1 2001

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Intellectual Property
Intellectual property
Test Generation
Built-in self test
Observability
Controllability
Partitioning
Logic
Internal
Line
Demonstrate

All Science Journal Classification (ASJC) codes

  • Signal Processing
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Hierarchical intellectual property protection using partially-mergeable cores. / Iyengar, Vikram; Date, Hiroshi; Sugihara, Makoto; Chakrabarty, Krishnendu.

In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E84-A, No. 11, 01.01.2001, p. 2632-2638.

Research output: Contribution to journalArticle

Iyengar, Vikram ; Date, Hiroshi ; Sugihara, Makoto ; Chakrabarty, Krishnendu. / Hierarchical intellectual property protection using partially-mergeable cores. In: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2001 ; Vol. E84-A, No. 11. pp. 2632-2638.
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