High-density room-temperature 3D chip-stacking using mechanical caulking with compliant bump and through-hole-electrode

Naoya Watanabe, Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Tanemasa Asano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this study, we employ a novel compliant bump in 3D chip-stacking using mechanical caulking. The compliant bump prepared in this work has a cone-like structure and is made of. Au. It is fabricated using an "undercut resist method," which combines undercut resist pattern formation with electroplating. The size of the compliant bump (approximately 10-30 μm in diameter) is much smaller than that of the stud bump. We demonstrate that by using a mechanical caulking process with a compliant bump and a through-hole-electrode, high-density through-hole-electrode interconnection (I/O number: 8,000, pitch: 20 μm) becomes possible, even at room temperature.

Original languageEnglish
Title of host publicationProceedings of the ASME InterPack Conference 2009, IPACK2009
Pages33-38
Number of pages6
DOIs
Publication statusPublished - Jun 25 2010
Event2009 ASME InterPack Conference, IPACK2009 - San Francisco, CA, United States
Duration: Jul 19 2009Jul 23 2009

Publication series

NameProceedings of the ASME InterPack Conference 2009, IPACK2009
Volume1

Other

Other2009 ASME InterPack Conference, IPACK2009
CountryUnited States
CitySan Francisco, CA
Period7/19/097/23/09

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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