High Efficiency and Small Group Delay Variations 0.18-μ m CMOS UWB Power Amplifier

Hamed Mosalam, A. Allam, Hongting Jia, A. B. Abdel-Rahman, Ramesh K. Pokharel

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

A new staggered tuning technique, by optimizing the inter-stage matching circuit, is proposed to realize a power amplifier (PA) with small group delay (GD) variations and excellent gain flatness across the full bandwidth of ultra-wideband (UWB) system. The proposed PA consists of two stages where the first stage is constructed by a current-reuse with shunt RC feedback topology to realize gain flatness and low power consumption. The design is implemented in 0.18 μ m commentary metal-oxide semiconductor (CMOS) technology, fabricated, and tested. The proposed PA has a measured power gain (|S 21 |) of 11.5 ± 0.7 dB, maximum power-added efficiency (PAE) of 26% and an output 1-dB compression point of 9 dBm, respectively, and this is the maximum PAE among CMOS PAs that cover the full bandwidth of UWB system. Besides, the PA has a small GD variations of ± 68 ps which is the lowest till date.

Original languageEnglish
Article number8464178
Pages (from-to)592-596
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume66
Issue number4
DOIs
Publication statusPublished - Apr 2019

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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