High-efficiency CMOS push-pull power amplifier with multilayer center-tapped transformer

Shingo Nakamura, Daisuke Kanemoto, Tomoki Sadakiyo, Haruichi Kanaya

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper describes the design of a push-pull power amplifier (PA) with a center-tapped transformer for transmitter applications on the 5.2-GHz band using 0.18μm CMOS technology. The type of the proposed PA is based on a double-ended push-pull (DEPP) configuration. DEPP has a simple construction with only transistors and transformers. The PA has reverse-phased cascode-connected transistors. The proposed transformer has a multilayer structure and was designed using electromagnetic field simulation. To achieve high power added efficiency (PAE), we assumed the optimized output impedance technique with a tunable impedance antenna. The PA has 13.2 dB linearity gain, 14.9 dBm 1-dB compression point (P1dB), and 27.4% maximum PAE.

Original languageEnglish
Pages (from-to)384-386
Number of pages3
JournalIEEJ Transactions on Electrical and Electronic Engineering
Volume11
Issue number3
DOIs
Publication statusPublished - May 1 2016
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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