High-efficiency CMOS push-pull power amplifier with multilayer center-tapped transformer

Shingo Nakamura; Daisuke Kanemoto; Tomoki Sadakiyo; Haruichi Kanaya

doi:10.1002/tee.22228

High-efficiency CMOS push-pull power amplifier with multilayer center-tapped transformer

Shingo Nakamura, Daisuke Kanemoto, Tomoki Sadakiyo, Haruichi Kanaya

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

This paper describes the design of a push-pull power amplifier (PA) with a center-tapped transformer for transmitter applications on the 5.2-GHz band using 0.18μm CMOS technology. The type of the proposed PA is based on a double-ended push-pull (DEPP) configuration. DEPP has a simple construction with only transistors and transformers. The PA has reverse-phased cascode-connected transistors. The proposed transformer has a multilayer structure and was designed using electromagnetic field simulation. To achieve high power added efficiency (PAE), we assumed the optimized output impedance technique with a tunable impedance antenna. The PA has 13.2 dB linearity gain, 14.9 dBm 1-dB compression point (P1dB), and 27.4% maximum PAE.

Original language	English
Pages (from-to)	384-386
Number of pages	3
Journal	IEEJ Transactions on Electrical and Electronic Engineering
Volume	11
Issue number	3
DOIs	https://doi.org/10.1002/tee.22228
Publication status	Published - May 1 2016
Externally published	Yes

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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10.1002/tee.22228

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title = "High-efficiency CMOS push-pull power amplifier with multilayer center-tapped transformer",

abstract = "This paper describes the design of a push-pull power amplifier (PA) with a center-tapped transformer for transmitter applications on the 5.2-GHz band using 0.18μm CMOS technology. The type of the proposed PA is based on a double-ended push-pull (DEPP) configuration. DEPP has a simple construction with only transistors and transformers. The PA has reverse-phased cascode-connected transistors. The proposed transformer has a multilayer structure and was designed using electromagnetic field simulation. To achieve high power added efficiency (PAE), we assumed the optimized output impedance technique with a tunable impedance antenna. The PA has 13.2 dB linearity gain, 14.9 dBm 1-dB compression point (P1dB), and 27.4% maximum PAE.",

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AU - Nakamura, Shingo

AU - Kanemoto, Daisuke

AU - Sadakiyo, Tomoki

AU - Kanaya, Haruichi

PY - 2016/5/1

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N2 - This paper describes the design of a push-pull power amplifier (PA) with a center-tapped transformer for transmitter applications on the 5.2-GHz band using 0.18μm CMOS technology. The type of the proposed PA is based on a double-ended push-pull (DEPP) configuration. DEPP has a simple construction with only transistors and transformers. The PA has reverse-phased cascode-connected transistors. The proposed transformer has a multilayer structure and was designed using electromagnetic field simulation. To achieve high power added efficiency (PAE), we assumed the optimized output impedance technique with a tunable impedance antenna. The PA has 13.2 dB linearity gain, 14.9 dBm 1-dB compression point (P1dB), and 27.4% maximum PAE.

AB - This paper describes the design of a push-pull power amplifier (PA) with a center-tapped transformer for transmitter applications on the 5.2-GHz band using 0.18μm CMOS technology. The type of the proposed PA is based on a double-ended push-pull (DEPP) configuration. DEPP has a simple construction with only transistors and transformers. The PA has reverse-phased cascode-connected transistors. The proposed transformer has a multilayer structure and was designed using electromagnetic field simulation. To achieve high power added efficiency (PAE), we assumed the optimized output impedance technique with a tunable impedance antenna. The PA has 13.2 dB linearity gain, 14.9 dBm 1-dB compression point (P1dB), and 27.4% maximum PAE.

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High-efficiency CMOS push-pull power amplifier with multilayer center-tapped transformer

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