High launch switching activity reduction in at-speed scan testing using CTX: A clock-gating-based test relaxation and x-filling scheme

Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung Terng Wang, Mohammad Tehranipoor

Research output: Contribution to journalArticlepeer-review

Abstract

At-speed scan testing is susceptible to yield loss risk due to power supply noise caused by excessive launch switching activity. This paper proposes a novel two-stage scheme, namely CTX (Clock-Gating-Based Test Relaxation and X-Filling), for reducing switching activity when a test stimulus is launched. Test relaxation and X-filling are conducted (1) to make as many FFs as possible inactive by disabling corresponding clock control signals of clock-gating circuitry in Stage-1 (Clock- Disabling), and (2) to equalize the input and output values in Stage-2 of as many remaining active FFs as possible (FF-Silencing). CTX effectively reduces launch switching activity and thus yield loss risk even when only a small number of don't care (X) bits are present (as in test compression) without any impact on test data volume, fault coverage, performance, or circuit design.

Original languageEnglish
Pages (from-to)2-9
Number of pages8
JournalIEICE Transactions on Information and Systems
VolumeE93-D
Issue number1
DOIs
Publication statusPublished - 2010

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Vision and Pattern Recognition
  • Electrical and Electronic Engineering
  • Artificial Intelligence

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