High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology

A. I.A. Galal, R. Pokharel, H. Kanaya, K. Yoshida

Research output: Contribution to journalArticle

13 Citations (Scopus)

Abstract

A linearization technique for ultra-wideband low noise amplifier (UWB LNA) has been designed and fabricated in standard 0.18 μm CMOS technology. The proposed technique exploits the complementary characteristics of NMOS and PMOS to improve the linearity performance. A two-stage UWB LNA is optimized to achieve high linearity over the 3.1-10.6 GHz range. The first stage adopts inverter topology with resistive feedback to provide high linearity and wideband input matching, whereas the second stage is a cascode amplifier with series and shunt inductive peaking techniques to extend the bandwidth and achieve high gain simultaneously. The proposed UWB LNA exhibits a measured flat gain of 15 dB within the entire band, a minimum noise figure of 3.5 dB, and an IIP3 of 6.4 dBm while consuming 8 mA from a 1.8 V power supply. The total chip area is 0.39 mm2, including all pads. The measured input return loss is kept below -11 dB, and the output return loss is -8 dB, from 3.1 to 10.6 GHz.

Original languageEnglish
Pages (from-to)12-17
Number of pages6
JournalAEU - International Journal of Electronics and Communications
Volume66
Issue number1
DOIs
Publication statusPublished - Jan 1 2012

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Broadband amplifiers
Low noise amplifiers
Ultra-wideband (UWB)
Noise figure
Linearization
Topology
Feedback
Bandwidth

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

High linearity technique for ultra-wideband low noise amplifier in 0.18 μm CMOS technology. / Galal, A. I.A.; Pokharel, R.; Kanaya, H.; Yoshida, K.

In: AEU - International Journal of Electronics and Communications, Vol. 66, No. 1, 01.01.2012, p. 12-17.

Research output: Contribution to journalArticle

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