TY - JOUR
T1 - High-sensitivity measurement of thermal deformation in a stacked multichip package
AU - Morita, Yasuyuki
AU - Arakawa, Kazuo
AU - Todo, Mitsugu
N1 - Funding Information:
Manuscript received August 4, 2005; revised July 25, 2006. This work was supported by a grant from the Shorai Foundation for Science and Technology. This work was recommended for publication by Associate Editor R. Chanchani upon evaluation of the reviewers’ comments.
PY - 2007/3
Y1 - 2007/3
N2 - The thermal deformation of a stacked multichip package, which is a newly developed electronic package, was measured by phase-shifting moiréinterferometry. We developed this method using a wedged glass plate as a phase shifter to obtain displacement fields having a sensitivity of 30 nm/line. This method also enabled the quantitative determination of the strain distributions in all observation areas. Thermal loading was applied from room temperature (25 °C) to elevated temperatures of 75 °C and 100 °C where the thermal strains were examined and compared. The results showed that the longitudinal strain εxx was concentrated at the ends of two silicon chips, and the longitudinal strain εyy increased between the two silicon chips. The shear strain γxy increased at the end of the lower silicon chip from 0.17% to 0.30% when the temperature increased by 25 °C.
AB - The thermal deformation of a stacked multichip package, which is a newly developed electronic package, was measured by phase-shifting moiréinterferometry. We developed this method using a wedged glass plate as a phase shifter to obtain displacement fields having a sensitivity of 30 nm/line. This method also enabled the quantitative determination of the strain distributions in all observation areas. Thermal loading was applied from room temperature (25 °C) to elevated temperatures of 75 °C and 100 °C where the thermal strains were examined and compared. The results showed that the longitudinal strain εxx was concentrated at the ends of two silicon chips, and the longitudinal strain εyy increased between the two silicon chips. The shear strain γxy increased at the end of the lower silicon chip from 0.17% to 0.30% when the temperature increased by 25 °C.
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U2 - 10.1109/TCAPT.2007.892093
DO - 10.1109/TCAPT.2007.892093
M3 - Article
AN - SCOPUS:34147175417
VL - 30
SP - 137
EP - 143
JO - IEEE Transactions on Components and Packaging Technologies
JF - IEEE Transactions on Components and Packaging Technologies
SN - 1521-3331
IS - 1
ER -