High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima

Research output: Contribution to journalArticlepeer-review

240 Citations (Scopus)

Abstract

A high-speed VLSI multiplication algorithm internally using redundant binary representation is proposed. In n bit binary integer multiplication, n partial products are first generated and then added up pairwise by means of a binary tree of redundant binary adders. Since parallel addition of two n-digitredundant binary numbers can be performed in a constant time independent of n without carry propagation, n bit multiplication can be performed in a time proportional to log2n. Thecomputation time is almost the same as that by a multiplier with a Wallace tree, in which three partial products will be converted into two, in contrast to our two-to-one conversion, and is much shorter than that by an array multiplier for longer operands. The number of computation elements of an n bit multiplier based on the algorithm is proportional to n2It is almost the same as those of conventional ones. Furthermore, since the multiplier has a regular cellular array structure similar to an array multiplier, it is suitable for VLSI implementation. Thus, the multiplier is excellent in both computation speed and regularity in layout. It can be implemented on a VLSI chip with an area proportional to n2log2n. The algorithm can be directly applied to both unsigned and 2's complement binary integer multiplication.

Original languageEnglish
Pages (from-to)789-796
Number of pages8
JournalIEEE Transactions on Computers
VolumeC-34
Issue number9
DOIs
Publication statusPublished - 1985
Externally publishedYes

All Science Journal Classification (ASJC) codes

  • Computational Theory and Mathematics
  • Hardware and Architecture
  • Software
  • Theoretical Computer Science
  • Electrical and Electronic Engineering

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