Highly reliable Cu/low-k dual-damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65 nm-node high performance eDRAM

A. Kajita, T. Usui, M. Yamada, E. Ogawa, T. Katata, A. Sakata, H. Miyajima, A. Kojima, R. Kanamura, Y. Ohoka, H. Kawashima, K. Tabuchi, K. Nagahata, Y. Kato, T. Hayashi, S. Kadomura, H. Shibata

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Citations (Scopus)

Abstract

100 nm half-pitch Cu dual-damascene (DD) interconnects with low-k hybrid (PAE(k2.65)/SiOC(k2.5)/SiC(k3.5)) dielectrics have been successfully integrated for a 65 nm-node high performance embedded DRAM. The hybrid-DD structure was fabricated by applying a hard mask process combined with Stacked Mask Process (S-MAP). Well-controlled DD profile of the hybrid structure can provide the advantage of void-less Cu fill, resulting from over-hang reduction of PVD barrier metal. Stress-induced voiding (SiV), which is becoming a more serious problem with down scaling of via-hole dimension was found to be drastically improved as compared with homogeneous-DD structures. Thermal cycle test (TCT) also shows no degradation of the wiring/via-hole properties. Moreover, the result of electromigration (EM) test shows a tight distribution of mean time to failure (MTF). The hybrid-DD structure can extend the PVD Cu filling process to 65 nm-node Cu metallization with excellent reliability.

Original languageEnglish
Title of host publicationProceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages9-11
Number of pages3
ISBN (Electronic)0780377974, 9780780377974
DOIs
Publication statusPublished - Jan 1 2003
Externally publishedYes
Event2003 IEEE International Interconnect Technology Conference, IITC 2003 - Burlingame, United States
Duration: Jun 2 2003Jun 4 2003

Publication series

NameProceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003

Other

Other2003 IEEE International Interconnect Technology Conference, IITC 2003
CountryUnited States
CityBurlingame
Period6/2/036/4/03

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Kajita, A., Usui, T., Yamada, M., Ogawa, E., Katata, T., Sakata, A., ... Shibata, H. (2003). Highly reliable Cu/low-k dual-damascene interconnect technology with hybrid (PAE/SiOC) dielectrics for 65 nm-node high performance eDRAM. In Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003 (pp. 9-11). [1219697] (Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IITC.2003.1219697