TY - GEN
T1 - Hybrid compile and run-time memory management for a 3D-stacked reconfigurable accelerator
AU - Gauthier, Lovic
AU - Ueno, Shinya
AU - Inoue, Koji
N1 - Copyright:
Copyright 2014 Elsevier B.V., All rights reserved.
PY - 2013
Y1 - 2013
N2 - This paper presents a hybrid compile and run-time memory management technique for a 3D-stacked reconfigurable accelerator including a memory layer composed of multiple memory units whose parallel access allows a very high bandwidth. The technique inserts allocation, free and data transfers into the code for using the memory layer and avoids memory overflows by adding a limited number of additional copies to and from the host memory. When compile-time information is lacking, the technique relies on run-time decisions for controlling these memory operations. Experiments show that, compared to a pessimistic approach, the overhead for avoiding overflows can be cut on average by 27%, 45% and 63% when the size of each memory unit is respectively 1kB, 128kB and 1MB.
AB - This paper presents a hybrid compile and run-time memory management technique for a 3D-stacked reconfigurable accelerator including a memory layer composed of multiple memory units whose parallel access allows a very high bandwidth. The technique inserts allocation, free and data transfers into the code for using the memory layer and avoids memory overflows by adding a limited number of additional copies to and from the host memory. When compile-time information is lacking, the technique relies on run-time decisions for controlling these memory operations. Experiments show that, compared to a pessimistic approach, the overhead for avoiding overflows can be cut on average by 27%, 45% and 63% when the size of each memory unit is respectively 1kB, 128kB and 1MB.
UR - http://www.scopus.com/inward/record.url?scp=84892638573&partnerID=8YFLogxK
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U2 - 10.1109/CASES.2013.6662514
DO - 10.1109/CASES.2013.6662514
M3 - Conference contribution
AN - SCOPUS:84892638573
SN - 9781479914005
T3 - 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013
BT - 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013
PB - IEEE Computer Society
T2 - 2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013
Y2 - 29 September 2013 through 4 October 2013
ER -