Hybrid compile and run-time memory management for a 3D-stacked reconfigurable accelerator

Lovic Gauthier, Shinya Ueno, Koji Inoue

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a hybrid compile and run-time memory management technique for a 3D-stacked reconfigurable accelerator including a memory layer composed of multiple memory units whose parallel access allows a very high bandwidth. The technique inserts allocation, free and data transfers into the code for using the memory layer and avoids memory overflows by adding a limited number of additional copies to and from the host memory. When compile-time information is lacking, the technique relies on run-time decisions for controlling these memory operations. Experiments show that, compared to a pessimistic approach, the overhead for avoiding overflows can be cut on average by 27%, 45% and 63% when the size of each memory unit is respectively 1kB, 128kB and 1MB.

Original languageEnglish
Title of host publication2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013
PublisherIEEE Computer Society
ISBN (Print)9781479914005
DOIs
Publication statusPublished - 2013
Event2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013 - Montreal, QC, Canada
Duration: Sep 29 2013Oct 4 2013

Publication series

Name2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013

Other

Other2013 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2013
CountryCanada
CityMontreal, QC
Period9/29/1310/4/13

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Control and Systems Engineering

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