Imprint lithography using triple-layer-resist and its application to metal-oxide-silicon field-effect-transisor fabrication

Hiroyuki Nakamura, Akiyoshi Baba, Tanemasa Asano

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

Imprint lithography using a triple-layer resist technique has been investigated. The triple-layer resist consisted of either novolac resin or polymethylmethacrylate (PMMA) for the top layer, Al for the intermediate layer, and novolac resin for the bottom layer. Molds made of crystal Si or porous-Si covered Si were prepared. The pattern transfer characteristic depending on pressure, substrate temperature during imprint, and mold material was investigated. It is found that imprinting at a substrate temperature close to the pre-bake temperature for the top resist is preferred for pattern transfer with high accuracy. The use of porous Si covered molds is shown to be effective for improving the uniformity. PMMA which has a relatively low glass-transition temperature is found to decrease the pressure required for the pattern transfer. It is also shown that mechanical stress applied to metal-oxide-silicon (MOS) capacitors does not affect the gate oxide integrity, as it is evaluated by time-dependent dielectric-breakdown. MOS field-effect transistors (MOSFETs) on SOI silicon-on-insulator (SOI) having the gate length of about 0.1 μm are fabricated using the imprint lithography. It is shown that imprint lithography does not degrade the performance of MOSFETs.

Original languageEnglish
Pages (from-to)7080-7085
Number of pages6
JournalJapanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers
Volume39
Issue number12 B
DOIs
Publication statusPublished - Dec 2000

All Science Journal Classification (ASJC) codes

  • Engineering(all)
  • Physics and Astronomy(all)

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