Imprint lithography using triple-layer-resist and its application to MOSFET fabrication

Hiroyuki Nakamura, Akiyoshi Baba, Tanemasa Asano

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we report pattern transfer characteristic of the imprint lithography by employing a triple-layer-resist method. In addition, fabrication of MOSFETs having the gate length down to 100 nm is demonstrated. Gate oxide integrity is also tested in order to investigate mechanical damage of the imprint stress on devices.

Original languageEnglish
Title of host publicationDigest of Papers - 2000 International Microprocesses and Nanotechnology Conference, MNC 2000
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages232-233
Number of pages2
ISBN (Electronic)4891140046, 9784891140045
DOIs
Publication statusPublished - Jan 1 2000
Externally publishedYes
EventInternational Microprocesses and Nanotechnology Conference, MNC 2000 - Tokyo, Japan
Duration: Jul 11 2000Jul 13 2000

Other

OtherInternational Microprocesses and Nanotechnology Conference, MNC 2000
CountryJapan
CityTokyo
Period7/11/007/13/00

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All Science Journal Classification (ASJC) codes

  • Biotechnology
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Nakamura, H., Baba, A., & Asano, T. (2000). Imprint lithography using triple-layer-resist and its application to MOSFET fabrication. In Digest of Papers - 2000 International Microprocesses and Nanotechnology Conference, MNC 2000 (pp. 232-233). [872730] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IMNC.2000.872730