Imprint lithography using triple-layer-resist and its application to MOSFET fabrication

Hiroyuki Nakamura; Akiyoshi Baba; Tanemasa Asano

doi:10.1109/IMNC.2000.872730

Imprint lithography using triple-layer-resist and its application to MOSFET fabrication

Hiroyuki Nakamura, Akiyoshi Baba, Tanemasa Asano

Center for Japan-Egypt Cooperation in Science and Technology（E-JUST Center）

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we report pattern transfer characteristic of the imprint lithography by employing a triple-layer-resist method. In addition, fabrication of MOSFETs having the gate length down to 100 nm is demonstrated. Gate oxide integrity is also tested in order to investigate mechanical damage of the imprint stress on devices.

Original language	English
Title of host publication	Digest of Papers - 2000 International Microprocesses and Nanotechnology Conference, MNC 2000
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	232-233
Number of pages	2
ISBN (Electronic)	4891140046, 9784891140045
DOIs	https://doi.org/10.1109/IMNC.2000.872730
Publication status	Published - Jan 1 2000
Event	International Microprocesses and Nanotechnology Conference, MNC 2000 - Tokyo, Japan Duration: Jul 11 2000 → Jul 13 2000

Other

Other	International Microprocesses and Nanotechnology Conference, MNC 2000
Country/Territory	Japan
City	Tokyo
Period	7/11/00 → 7/13/00

All Science Journal Classification (ASJC) codes

Biotechnology
Electrical and Electronic Engineering
Electronic, Optical and Magnetic Materials

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10.1109/IMNC.2000.872730

Cite this

Imprint lithography using triple-layer-resist and its application to MOSFET fabrication. / Nakamura, Hiroyuki; Baba, Akiyoshi; Asano, Tanemasa.
Digest of Papers - 2000 International Microprocesses and Nanotechnology Conference, MNC 2000. Institute of Electrical and Electronics Engineers Inc., 2000. p. 232-233 872730.

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Nakamura, H, Baba, A & Asano, T 2000, Imprint lithography using triple-layer-resist and its application to MOSFET fabrication. in Digest of Papers - 2000 International Microprocesses and Nanotechnology Conference, MNC 2000., 872730, Institute of Electrical and Electronics Engineers Inc., pp. 232-233, International Microprocesses and Nanotechnology Conference, MNC 2000, Tokyo, Japan, 7/11/00. https://doi.org/10.1109/IMNC.2000.872730

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title = "Imprint lithography using triple-layer-resist and its application to MOSFET fabrication",

abstract = "In this paper, we report pattern transfer characteristic of the imprint lithography by employing a triple-layer-resist method. In addition, fabrication of MOSFETs having the gate length down to 100 nm is demonstrated. Gate oxide integrity is also tested in order to investigate mechanical damage of the imprint stress on devices.",

author = "Hiroyuki Nakamura and Akiyoshi Baba and Tanemasa Asano",

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doi = "10.1109/IMNC.2000.872730",

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Y1 - 2000/1/1

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AB - In this paper, we report pattern transfer characteristic of the imprint lithography by employing a triple-layer-resist method. In addition, fabrication of MOSFETs having the gate length down to 100 nm is demonstrated. Gate oxide integrity is also tested in order to investigate mechanical damage of the imprint stress on devices.

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BT - Digest of Papers - 2000 International Microprocesses and Nanotechnology Conference, MNC 2000

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - International Microprocesses and Nanotechnology Conference, MNC 2000

Y2 - 11 July 2000 through 13 July 2000

ER -

Imprint lithography using triple-layer-resist and its application to MOSFET fabrication

Abstract

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All Science Journal Classification (ASJC) codes

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