TY - JOUR
T1 - Improved gain 60GHz CMOS antenna with N-well grid
AU - Barakat, Adel
AU - Allam, Ahmed
AU - Elsadek, Hala
AU - Abdel-Rahman, Adel B.
AU - Pokharel, Ramesh K.
AU - Kaho, Takana
N1 - Publisher Copyright:
© IEICE 2016.
Copyright:
Copyright 2020 Elsevier B.V., All rights reserved.
PY - 2016/2/19
Y1 - 2016/2/19
N2 - This paper presents a novel technique to enhance Antenna-on- Chip gain by introducing a high resistivity layer below it. Instead of using the costly ion implantation method to increase resistivity, the N-well that is available in the standard CMOS process is used. A distributed grid structure of N-well on P-type substrate is designed such that the P and N semiconductors types are fully depleted forming a layer with high resistivity. By an electromagnetic simulation, the using depletion layers enhance the antenna gain and radiation efficiency without increasing the occupied area. The simulated and measured |S11| are in fair agreement. The measured gain is −1.5 dBi at 66 GHz.
AB - This paper presents a novel technique to enhance Antenna-on- Chip gain by introducing a high resistivity layer below it. Instead of using the costly ion implantation method to increase resistivity, the N-well that is available in the standard CMOS process is used. A distributed grid structure of N-well on P-type substrate is designed such that the P and N semiconductors types are fully depleted forming a layer with high resistivity. By an electromagnetic simulation, the using depletion layers enhance the antenna gain and radiation efficiency without increasing the occupied area. The simulated and measured |S11| are in fair agreement. The measured gain is −1.5 dBi at 66 GHz.
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U2 - 10.1587/elex.13.20151115
DO - 10.1587/elex.13.20151115
M3 - Article
AN - SCOPUS:84960423056
VL - 13
JO - IEICE Electronics Express
JF - IEICE Electronics Express
SN - 1349-2543
IS - 5
M1 - 20151115
ER -