Improved gain 60GHz CMOS antenna with N-well grid

Adel Barakat, Ahmed Allam, Hala Elsadek, Adel B. Abdel-Rahman, Ramesh K. Pokharel, Takana Kaho

Research output: Contribution to journalLetter

1 Citation (Scopus)

Abstract

This paper presents a novel technique to enhance Antenna-on- Chip gain by introducing a high resistivity layer below it. Instead of using the costly ion implantation method to increase resistivity, the N-well that is available in the standard CMOS process is used. A distributed grid structure of N-well on P-type substrate is designed such that the P and N semiconductors types are fully depleted forming a layer with high resistivity. By an electromagnetic simulation, the using depletion layers enhance the antenna gain and radiation efficiency without increasing the occupied area. The simulated and measured |S11| are in fair agreement. The measured gain is −1.5 dBi at 66 GHz.

Original languageEnglish
JournalIEICE Electronics Express
Volume13
Issue number5
DOIs
Publication statusPublished - Feb 19 2016

Fingerprint

CMOS
antennas
grids
Antennas
electrical resistivity
Ion implantation
antenna gain
Semiconductor materials
Radiation
ion implantation
depletion
Substrates
chips
electromagnetism
radiation
simulation

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Barakat, A., Allam, A., Elsadek, H., Abdel-Rahman, A. B., Pokharel, R. K., & Kaho, T. (2016). Improved gain 60GHz CMOS antenna with N-well grid. IEICE Electronics Express, 13(5). https://doi.org/10.1587/elex.13.20151115

Improved gain 60GHz CMOS antenna with N-well grid. / Barakat, Adel; Allam, Ahmed; Elsadek, Hala; Abdel-Rahman, Adel B.; Pokharel, Ramesh K.; Kaho, Takana.

In: IEICE Electronics Express, Vol. 13, No. 5, 19.02.2016.

Research output: Contribution to journalLetter

Barakat, A, Allam, A, Elsadek, H, Abdel-Rahman, AB, Pokharel, RK & Kaho, T 2016, 'Improved gain 60GHz CMOS antenna with N-well grid', IEICE Electronics Express, vol. 13, no. 5. https://doi.org/10.1587/elex.13.20151115
Barakat, Adel ; Allam, Ahmed ; Elsadek, Hala ; Abdel-Rahman, Adel B. ; Pokharel, Ramesh K. ; Kaho, Takana. / Improved gain 60GHz CMOS antenna with N-well grid. In: IEICE Electronics Express. 2016 ; Vol. 13, No. 5.
@article{8301b29ef5fd4e92828a1be0eb73ab07,
title = "Improved gain 60GHz CMOS antenna with N-well grid",
abstract = "This paper presents a novel technique to enhance Antenna-on- Chip gain by introducing a high resistivity layer below it. Instead of using the costly ion implantation method to increase resistivity, the N-well that is available in the standard CMOS process is used. A distributed grid structure of N-well on P-type substrate is designed such that the P and N semiconductors types are fully depleted forming a layer with high resistivity. By an electromagnetic simulation, the using depletion layers enhance the antenna gain and radiation efficiency without increasing the occupied area. The simulated and measured |S11| are in fair agreement. The measured gain is −1.5 dBi at 66 GHz.",
author = "Adel Barakat and Ahmed Allam and Hala Elsadek and Abdel-Rahman, {Adel B.} and Pokharel, {Ramesh K.} and Takana Kaho",
year = "2016",
month = "2",
day = "19",
doi = "10.1587/elex.13.20151115",
language = "English",
volume = "13",
journal = "IEICE Electronics Express",
issn = "1349-2543",
publisher = "The Institute of Electronics, Information and Communication Engineers (IEICE)",
number = "5",

}

TY - JOUR

T1 - Improved gain 60GHz CMOS antenna with N-well grid

AU - Barakat, Adel

AU - Allam, Ahmed

AU - Elsadek, Hala

AU - Abdel-Rahman, Adel B.

AU - Pokharel, Ramesh K.

AU - Kaho, Takana

PY - 2016/2/19

Y1 - 2016/2/19

N2 - This paper presents a novel technique to enhance Antenna-on- Chip gain by introducing a high resistivity layer below it. Instead of using the costly ion implantation method to increase resistivity, the N-well that is available in the standard CMOS process is used. A distributed grid structure of N-well on P-type substrate is designed such that the P and N semiconductors types are fully depleted forming a layer with high resistivity. By an electromagnetic simulation, the using depletion layers enhance the antenna gain and radiation efficiency without increasing the occupied area. The simulated and measured |S11| are in fair agreement. The measured gain is −1.5 dBi at 66 GHz.

AB - This paper presents a novel technique to enhance Antenna-on- Chip gain by introducing a high resistivity layer below it. Instead of using the costly ion implantation method to increase resistivity, the N-well that is available in the standard CMOS process is used. A distributed grid structure of N-well on P-type substrate is designed such that the P and N semiconductors types are fully depleted forming a layer with high resistivity. By an electromagnetic simulation, the using depletion layers enhance the antenna gain and radiation efficiency without increasing the occupied area. The simulated and measured |S11| are in fair agreement. The measured gain is −1.5 dBi at 66 GHz.

UR - http://www.scopus.com/inward/record.url?scp=84960423056&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84960423056&partnerID=8YFLogxK

U2 - 10.1587/elex.13.20151115

DO - 10.1587/elex.13.20151115

M3 - Letter

AN - SCOPUS:84960423056

VL - 13

JO - IEICE Electronics Express

JF - IEICE Electronics Express

SN - 1349-2543

IS - 5

ER -