Instruction encoding techniques for area minimization of instruction ROM

T. Okuma, H. Tomiyama, A. Inoue, E. Fajar, H. Yasuura

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Citations (Scopus)

Abstract

In this paper we propose instruction encoding techniques for embedded system design, which encode immediate fields of instructions to reduce the size of an instruction memory. Although our proposed techniques require an additional decoder for the encoded immediate values, experimental results demonstrate the effectiveness of our techniques to reduce the chip area.

Original languageEnglish
Title of host publicationProceedings of the 11th International Symposium on System Synthesis, ISSS 1998
EditorsFrancky Catthoor
PublisherIEEE Computer Society
Pages125-130
Number of pages6
ISBN (Electronic)0818686235, 9780818686238
DOIs
Publication statusPublished - Dec 2 1998
Event11th International Symposium on System Synthesis, ISSS 1998 - Hsinchu, Taiwan, Province of China
Duration: Dec 2 1998Dec 4 1998

Publication series

NameProceedings of the International Symposium on System Synthesis
VolumePart F129250
ISSN (Print)1080-1820

Other

Other11th International Symposium on System Synthesis, ISSS 1998
CountryTaiwan, Province of China
CityHsinchu
Period12/2/9812/4/98

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture

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  • Cite this

    Okuma, T., Tomiyama, H., Inoue, A., Fajar, E., & Yasuura, H. (1998). Instruction encoding techniques for area minimization of instruction ROM. In F. Catthoor (Ed.), Proceedings of the 11th International Symposium on System Synthesis, ISSS 1998 (pp. 125-130). (Proceedings of the International Symposium on System Synthesis; Vol. Part F129250). IEEE Computer Society. https://doi.org/10.1109/isss.1998.730612