Instruction scheduling for power reduction in processor-based system design

Hiroyuki Tomiyama, Tohru Ishihara, Akihiko Inoue, Hiroto Yasuura

Research output: Contribution to journalConference article

24 Citations (Scopus)

Abstract

This paper proposes an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm.

Original languageEnglish
Article number655958
Pages (from-to)855-860
Number of pages6
JournalProceedings -Design, Automation and Test in Europe, DATE
DOIs
Publication statusPublished - Dec 1 1998
EventDesign, Automation and Test in Europe, DATE 1998 - Paris, France
Duration: Feb 23 1998Feb 26 1998

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Systems analysis
Scheduling
Scheduling algorithms
Data storage equipment

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Instruction scheduling for power reduction in processor-based system design. / Tomiyama, Hiroyuki; Ishihara, Tohru; Inoue, Akihiko; Yasuura, Hiroto.

In: Proceedings -Design, Automation and Test in Europe, DATE, 01.12.1998, p. 855-860.

Research output: Contribution to journalConference article

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