This paper proposes an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm.
|Number of pages||6|
|Journal||Proceedings -Design, Automation and Test in Europe, DATE|
|Publication status||Published - 1998|
|Event||Design, Automation and Test in Europe, DATE 1998 - Paris, France|
Duration: Feb 23 1998 → Feb 26 1998
All Science Journal Classification (ASJC) codes