Instruction scheduling to reduce switching activity of off-chip buses for low-power systems with caches

Computer Science

• Switching Activity 100%
• Instruction Scheduling 100%
• Algorithms 50%
• Experimental Result 50%
• Scheduling Problem 50%
• Embedded Systems 50%
• Scheduling Algorithm 50%
• Significant Amount 50%
• Main Memory 50%
• Instruction-Cache Miss 50%