Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit

Jun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)
Original languageEnglish
Title of host publication2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009
DOIs
Publication statusPublished - Sep 25 2009
Externally publishedYes
Event2009 IEEE International Solid-State Circuits Conference ISSCC 2009 - San Francisco, CA, United States
Duration: Feb 8 2009Feb 12 2009

Publication series

NameDigest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)0193-6530

Conference

Conference2009 IEEE International Solid-State Circuits Conference ISSCC 2009
CountryUnited States
CitySan Francisco, CA
Period2/8/092/12/09

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Terada, J., Ohtomo, Y., Nishimura, K., Katsurai, H., Kimura, S., & Yoshimoto, N. (2009). Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. In 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009 [4977329] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2009.4977329