Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit

Jun Terada; Yusuke Ohtomo; Kazuyoshi Nishimura; Hiroaki Katsurai; Shunji Kimura; Naoto Yoshimoto

doi:10.1109/ISSCC.2009.4977329

Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit

Jun Terada, Yusuke Ohtomo, Kazuyoshi Nishimura, Hiroaki Katsurai, Shunji Kimura, Naoto Yoshimoto

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Original language	English
Title of host publication	2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009
DOIs	https://doi.org/10.1109/ISSCC.2009.4977329
Publication status	Published - Sept 25 2009
Externally published	Yes
Event	2009 IEEE International Solid-State Circuits Conference ISSCC 2009 - San Francisco, CA, United States Duration: Feb 8 2009 → Feb 12 2009

Publication series

Name	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN (Print)	0193-6530

Conference

Conference	2009 IEEE International Solid-State Circuits Conference ISSCC 2009
Country/Territory	United States
City	San Francisco, CA
Period	2/8/09 → 2/12/09

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ISSCC.2009.4977329

Cite this

Terada, J., Ohtomo, Y., Nishimura, K., Katsurai, H., Kimura, S., & Yoshimoto, N. (2009). Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. In 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009 [4977329] (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). https://doi.org/10.1109/ISSCC.2009.4977329

Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. / Terada, Jun; Ohtomo, Yusuke; Nishimura, Kazuyoshi et al.
2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009. 2009. 4977329 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Terada, J, Ohtomo, Y, Nishimura, K, Katsurai, H, Kimura, S & Yoshimoto, N 2009, Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. in 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009., 4977329, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 2009 IEEE International Solid-State Circuits Conference ISSCC 2009, San Francisco, CA, United States, 2/8/09. https://doi.org/10.1109/ISSCC.2009.4977329

Terada J, Ohtomo Y, Nishimura K, Katsurai H, Kimura S, Yoshimoto N. Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit. In 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, ISSCC 2009. 2009. 4977329. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2009.4977329

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Jitter-reduction and pulse-width-distortion compensation circuits for a 10Gb/s burst-mode CDR circuit

Publication series

Conference

All Science Journal Classification (ASJC) codes

Access to Document

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Cite this