Structural and electronic properties of continuous grain (CG) silicon fabricated by the low temperature catalyst-assisted solid-phase crystallization, was investigated by comparing it with those of so-called low-temperature polycrystalline silicon (LTPS). CG silicon showed a very large domain size, up to 15 μm, whereas the size of conventional LTPS is typically less than 1 μm. Misorientation angles at the grain boundaries for CG silicon were found mostly to be less than 10° in contrast to that between 30 and 60° for the LTPS. In addition, the lattice images at the grain boundary of CG silicon are almost aligned regularly, leaving only a few-stacking faults. The trap state density at the grain boundaries was evaluated to be 4.5 × 1011/cm2 by the modified Levinson analysis of CG silicon thin-film transistors (TFTs), which is less than half of the value for the conventional LTPS. It was concluded that the CG silicon with larger domains and lower misoriented grain boundaries has significantly higher potential for the lower trap state density at the grain boundaries and higher performance of CG silicon-TFTs over the LTPS-TFTs.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering