Abstract
Structural and electronic properties of continuous grain (CG) silicon fabricated by the low temperature catalyst-assisted solid-phase crystallization, was investigated by comparing it with those of so-called low-temperature polycrystalline silicon (LTPS). CG silicon showed a very large domain size, up to 15 μm, whereas the size of conventional LTPS is typically less than 1 μm. Misorientation angles at the grain boundaries for CG silicon were found mostly to be less than 10° in contrast to that between 30 and 60° for the LTPS. In addition, the lattice images at the grain boundary of CG silicon are almost aligned regularly, leaving only a few-stacking faults. The trap state density at the grain boundaries was evaluated to be 4.5 × 1011/cm2 by the modified Levinson analysis of CG silicon thin-film transistors (TFTs), which is less than half of the value for the conventional LTPS. It was concluded that the CG silicon with larger domains and lower misoriented grain boundaries has significantly higher potential for the lower trap state density at the grain boundaries and higher performance of CG silicon-TFTs over the LTPS-TFTs.
| Original language | English |
|---|---|
| Pages (from-to) | 204-211 |
| Number of pages | 8 |
| Journal | IEEE Transactions on Electron Devices |
| Volume | 51 |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - Feb 1 2004 |
| Externally published | Yes |
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All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
Cite this
Large domains of continuous grain silicon on glass substrate for high-performance TFTs. / Mizuki, Toshio; Matsuda, Junko; Nakamura, Yoshinobu; Takagi, Junkoh; Yoshida, Toyonobu.
In: IEEE Transactions on Electron Devices, Vol. 51, No. 2, 01.02.2004, p. 204-211.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - Large domains of continuous grain silicon on glass substrate for high-performance TFTs
AU - Mizuki, Toshio
AU - Matsuda, Junko
AU - Nakamura, Yoshinobu
AU - Takagi, Junkoh
AU - Yoshida, Toyonobu
PY - 2004/2/1
Y1 - 2004/2/1
N2 - Structural and electronic properties of continuous grain (CG) silicon fabricated by the low temperature catalyst-assisted solid-phase crystallization, was investigated by comparing it with those of so-called low-temperature polycrystalline silicon (LTPS). CG silicon showed a very large domain size, up to 15 μm, whereas the size of conventional LTPS is typically less than 1 μm. Misorientation angles at the grain boundaries for CG silicon were found mostly to be less than 10° in contrast to that between 30 and 60° for the LTPS. In addition, the lattice images at the grain boundary of CG silicon are almost aligned regularly, leaving only a few-stacking faults. The trap state density at the grain boundaries was evaluated to be 4.5 × 1011/cm2 by the modified Levinson analysis of CG silicon thin-film transistors (TFTs), which is less than half of the value for the conventional LTPS. It was concluded that the CG silicon with larger domains and lower misoriented grain boundaries has significantly higher potential for the lower trap state density at the grain boundaries and higher performance of CG silicon-TFTs over the LTPS-TFTs.
AB - Structural and electronic properties of continuous grain (CG) silicon fabricated by the low temperature catalyst-assisted solid-phase crystallization, was investigated by comparing it with those of so-called low-temperature polycrystalline silicon (LTPS). CG silicon showed a very large domain size, up to 15 μm, whereas the size of conventional LTPS is typically less than 1 μm. Misorientation angles at the grain boundaries for CG silicon were found mostly to be less than 10° in contrast to that between 30 and 60° for the LTPS. In addition, the lattice images at the grain boundary of CG silicon are almost aligned regularly, leaving only a few-stacking faults. The trap state density at the grain boundaries was evaluated to be 4.5 × 1011/cm2 by the modified Levinson analysis of CG silicon thin-film transistors (TFTs), which is less than half of the value for the conventional LTPS. It was concluded that the CG silicon with larger domains and lower misoriented grain boundaries has significantly higher potential for the lower trap state density at the grain boundaries and higher performance of CG silicon-TFTs over the LTPS-TFTs.
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UR - http://www.scopus.com/inward/citedby.url?scp=0442326801&partnerID=8YFLogxK
U2 - 10.1109/TED.2003.821770
DO - 10.1109/TED.2003.821770
M3 - Article
AN - SCOPUS:0442326801
VL - 51
SP - 204
EP - 211
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
SN - 0018-9383
IS - 2
ER -