Line sharing cache: Exploring cache capacity with frequent line value locality

Keitarou Oka, Hiroshi Sasaki, Koji Inoue

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper proposes a new last level cache architecture called line sharing cache (LSC), which can reduce the number of cache misses without increasing the size of the cache memory. It stores lines which contain the identical value in a single line entry, which enables to store greater amount of lines. Evaluation results show performance improvements of up to 35% across a set of SPEC CPU2000 benchmarks.

Original languageEnglish
Title of host publication2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
Pages669-674
Number of pages6
DOIs
Publication statusPublished - May 20 2013
Event2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama, Japan
Duration: Jan 22 2013Jan 25 2013

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Other

Other2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
CountryJapan
CityYokohama
Period1/22/131/25/13

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'Line sharing cache: Exploring cache capacity with frequent line value locality'. Together they form a unique fingerprint.

Cite this