Logic BIST architecture using staggered launch-on-shift for testing designs containing asynchronous clock domains

Shianling Wu, Laung Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen Ben Jone, Nur A. Touba, Feifei Zhao, Jinsong Liu, Hao Jan Chao, Fangfang Li, Zhigang Jiang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

This paper presents a new at-speed logic built-in self-test (BIST) architecture using staggered launch-on-shift (LOS) for testing a scan-based BIST design containing asynchronous clock domains. The proposed approach can detect inter-clock-domain structural faults and intra-clock-domain delay and structural faults in the BIST design. This solves the long-standing problem of using the conventional one-hot LOS approach that requires testing one clock domain at a time which causes long test time or using the simultaneous LOS approach that requires adding capture-disabled circuitry to normal functional paths across interacting clock domains which causes fault coverage loss. Given a fixed number of BIST patterns, experimental results showed that the proposed staggered clocking scheme can detect more faults than one-hot clocking and simultaneous clocking.

Original languageEnglish
Title of host publicationProceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010
Pages358-366
Number of pages9
DOIs
Publication statusPublished - Dec 1 2010
Event2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010 - Kyoto, Japan
Duration: Oct 6 2010Oct 8 2010

Publication series

NameProceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
ISSN (Print)1550-5774

Other

Other2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010
CountryJapan
CityKyoto
Period10/6/1010/8/10

Fingerprint

Built-in self test
Clocks
Testing

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Wu, S., Wang, L. T., Yu, L., Furukawa, H., Wen, X., Jone, W. B., ... Jiang, Z. (2010). Logic BIST architecture using staggered launch-on-shift for testing designs containing asynchronous clock domains. In Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010 (pp. 358-366). [5634930] (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFT.2010.50

Logic BIST architecture using staggered launch-on-shift for testing designs containing asynchronous clock domains. / Wu, Shianling; Wang, Laung Terng; Yu, Lizhen; Furukawa, Hiroshi; Wen, Xiaoqing; Jone, Wen Ben; Touba, Nur A.; Zhao, Feifei; Liu, Jinsong; Chao, Hao Jan; Li, Fangfang; Jiang, Zhigang.

Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010. 2010. p. 358-366 5634930 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Wu, S, Wang, LT, Yu, L, Furukawa, H, Wen, X, Jone, WB, Touba, NA, Zhao, F, Liu, J, Chao, HJ, Li, F & Jiang, Z 2010, Logic BIST architecture using staggered launch-on-shift for testing designs containing asynchronous clock domains. in Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010., 5634930, Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 358-366, 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010, Kyoto, Japan, 10/6/10. https://doi.org/10.1109/DFT.2010.50
Wu S, Wang LT, Yu L, Furukawa H, Wen X, Jone WB et al. Logic BIST architecture using staggered launch-on-shift for testing designs containing asynchronous clock domains. In Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010. 2010. p. 358-366. 5634930. (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems). https://doi.org/10.1109/DFT.2010.50
Wu, Shianling ; Wang, Laung Terng ; Yu, Lizhen ; Furukawa, Hiroshi ; Wen, Xiaoqing ; Jone, Wen Ben ; Touba, Nur A. ; Zhao, Feifei ; Liu, Jinsong ; Chao, Hao Jan ; Li, Fangfang ; Jiang, Zhigang. / Logic BIST architecture using staggered launch-on-shift for testing designs containing asynchronous clock domains. Proceedings - 2010 25th International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2010. 2010. pp. 358-366 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems).
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AU - Jone, Wen Ben

AU - Touba, Nur A.

AU - Zhao, Feifei

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